/*
* VAS_EBOOT -- GRand Unified Bootloader
* Copyright (C) 2010 Free Software Foundation, Inc.
*
* VAS_EBOOT is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* VAS_EBOOT is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with VAS_EBOOT. If not, see .
*/
#include
#include
#include
#include
#include
#ifdef VAS_EBOOT_MACHINE_MIPS_LOONGSON
#include
#endif
#include
VAS_EBOOT_MOD_LICENSE ("GPLv3+");
/* Context for VasEBoot_cs5536_find. */
struct VasEBoot_cs5536_find_ctx
{
VasEBoot_pci_device_t *devp;
int found;
};
/* Helper for VasEBoot_cs5536_find. */
static int
VasEBoot_cs5536_find_iter (VasEBoot_pci_device_t dev, VasEBoot_pci_id_t pciid, void *data)
{
struct VasEBoot_cs5536_find_ctx *ctx = data;
if (pciid == VAS_EBOOT_CS5536_PCIID)
{
*ctx->devp = dev;
ctx->found = 1;
return 1;
}
return 0;
}
int
VasEBoot_cs5536_find (VasEBoot_pci_device_t *devp)
{
struct VasEBoot_cs5536_find_ctx ctx = {
.devp = devp,
.found = 0
};
VasEBoot_pci_iterate (VasEBoot_cs5536_find_iter, &ctx);
return ctx.found;
}
VasEBoot_uint64_t
VasEBoot_cs5536_read_msr (VasEBoot_pci_device_t dev, VasEBoot_uint32_t addr)
{
VasEBoot_uint64_t ret = 0;
VasEBoot_pci_write (VasEBoot_pci_make_address (dev, VAS_EBOOT_CS5536_MSR_MAILBOX_ADDR),
addr);
ret = (VasEBoot_uint64_t)
VasEBoot_pci_read (VasEBoot_pci_make_address (dev, VAS_EBOOT_CS5536_MSR_MAILBOX_DATA0));
ret |= (((VasEBoot_uint64_t)
VasEBoot_pci_read (VasEBoot_pci_make_address (dev,
VAS_EBOOT_CS5536_MSR_MAILBOX_DATA1)))
<< 32);
return ret;
}
void
VasEBoot_cs5536_write_msr (VasEBoot_pci_device_t dev, VasEBoot_uint32_t addr,
VasEBoot_uint64_t val)
{
VasEBoot_pci_write (VasEBoot_pci_make_address (dev, VAS_EBOOT_CS5536_MSR_MAILBOX_ADDR),
addr);
VasEBoot_pci_write (VasEBoot_pci_make_address (dev, VAS_EBOOT_CS5536_MSR_MAILBOX_DATA0),
val & 0xffffffff);
VasEBoot_pci_write (VasEBoot_pci_make_address (dev, VAS_EBOOT_CS5536_MSR_MAILBOX_DATA1),
val >> 32);
}
VasEBoot_err_t
VasEBoot_cs5536_smbus_wait (VasEBoot_port_t smbbase)
{
VasEBoot_uint64_t start = VasEBoot_get_time_ms ();
while (1)
{
VasEBoot_uint8_t status;
status = VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_STATUS);
if (status & VAS_EBOOT_CS5536_SMB_REG_STATUS_SDAST)
return VAS_EBOOT_ERR_NONE;
if (status & VAS_EBOOT_CS5536_SMB_REG_STATUS_BER)
return VasEBoot_error (VAS_EBOOT_ERR_IO, "SM bus error");
if (status & VAS_EBOOT_CS5536_SMB_REG_STATUS_NACK)
return VasEBoot_error (VAS_EBOOT_ERR_IO, "NACK received");
if (VasEBoot_get_time_ms () > start + 40)
return VasEBoot_error (VAS_EBOOT_ERR_IO, "SM stalled");
}
}
VasEBoot_err_t
VasEBoot_cs5536_read_spd_byte (VasEBoot_port_t smbbase, VasEBoot_uint8_t dev,
VasEBoot_uint8_t addr, VasEBoot_uint8_t *res)
{
VasEBoot_err_t err;
/* Send START. */
VasEBoot_outb (VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1)
| VAS_EBOOT_CS5536_SMB_REG_CTRL1_START,
smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1);
/* Send device address. */
err = VasEBoot_cs5536_smbus_wait (smbbase);
if (err)
return err;
VasEBoot_outb (dev << 1, smbbase + VAS_EBOOT_CS5536_SMB_REG_DATA);
/* Send ACK. */
err = VasEBoot_cs5536_smbus_wait (smbbase);
if (err)
return err;
VasEBoot_outb (VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1)
| VAS_EBOOT_CS5536_SMB_REG_CTRL1_ACK,
smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1);
/* Send byte address. */
VasEBoot_outb (addr, smbbase + VAS_EBOOT_CS5536_SMB_REG_DATA);
/* Send START. */
err = VasEBoot_cs5536_smbus_wait (smbbase);
if (err)
return err;
VasEBoot_outb (VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1)
| VAS_EBOOT_CS5536_SMB_REG_CTRL1_START,
smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1);
/* Send device address. */
err = VasEBoot_cs5536_smbus_wait (smbbase);
if (err)
return err;
VasEBoot_outb ((dev << 1) | 1, smbbase + VAS_EBOOT_CS5536_SMB_REG_DATA);
/* Send STOP. */
err = VasEBoot_cs5536_smbus_wait (smbbase);
if (err)
return err;
VasEBoot_outb (VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1)
| VAS_EBOOT_CS5536_SMB_REG_CTRL1_STOP,
smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1);
err = VasEBoot_cs5536_smbus_wait (smbbase);
if (err)
return err;
*res = VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_DATA);
return VAS_EBOOT_ERR_NONE;
}
VasEBoot_err_t
VasEBoot_cs5536_init_smbus (VasEBoot_pci_device_t dev, VasEBoot_uint16_t divisor,
VasEBoot_port_t *smbbase)
{
VasEBoot_uint64_t smbbar;
smbbar = VasEBoot_cs5536_read_msr (dev, VAS_EBOOT_CS5536_MSR_SMB_BAR);
/* FIXME */
if (!(smbbar & VAS_EBOOT_CS5536_LBAR_ENABLE))
return VasEBoot_error(VAS_EBOOT_ERR_IO, "SMB controller not enabled\n");
*smbbase = (smbbar & VAS_EBOOT_CS5536_LBAR_ADDR_MASK) + VAS_EBOOT_MACHINE_PCI_IO_BASE;
if (divisor < 8)
return VasEBoot_error (VAS_EBOOT_ERR_BAD_ARGUMENT, "invalid divisor");
/* Disable SMB. */
VasEBoot_outb (0, *smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL2);
/* Disable interrupts. */
VasEBoot_outb (0, *smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1);
/* Set as master. */
VasEBoot_outb (VAS_EBOOT_CS5536_SMB_REG_ADDR_MASTER,
*smbbase + VAS_EBOOT_CS5536_SMB_REG_ADDR);
/* Launch. */
VasEBoot_outb (((divisor >> 7) & 0xff), *smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL3);
VasEBoot_outb (((divisor << 1) & 0xfe) | VAS_EBOOT_CS5536_SMB_REG_CTRL2_ENABLE,
*smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL2);
return VAS_EBOOT_ERR_NONE;
}
VasEBoot_err_t
VasEBoot_cs5536_read_spd (VasEBoot_port_t smbbase, VasEBoot_uint8_t dev,
struct VasEBoot_smbus_spd *res)
{
VasEBoot_err_t err;
VasEBoot_size_t size;
VasEBoot_uint8_t b;
VasEBoot_size_t ptr;
err = VasEBoot_cs5536_read_spd_byte (smbbase, dev, 0, &b);
if (err)
return err;
if (b == 0)
return VasEBoot_error (VAS_EBOOT_ERR_IO, "no SPD found");
size = b;
((VasEBoot_uint8_t *) res)[0] = b;
for (ptr = 1; ptr < size; ptr++)
{
err = VasEBoot_cs5536_read_spd_byte (smbbase, dev, ptr,
&((VasEBoot_uint8_t *) res)[ptr]);
if (err)
return err;
}
return VAS_EBOOT_ERR_NONE;
}
static inline void
set_io_space (VasEBoot_pci_device_t dev, int num, VasEBoot_uint16_t start,
VasEBoot_uint16_t len)
{
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_GL_REGIONS_START + num,
((((VasEBoot_uint64_t) start + len - 4)
<< VAS_EBOOT_CS5536_MSR_GL_REGION_IO_TOP_SHIFT)
& VAS_EBOOT_CS5536_MSR_GL_REGION_TOP_MASK)
| (((VasEBoot_uint64_t) start
<< VAS_EBOOT_CS5536_MSR_GL_REGION_IO_BASE_SHIFT)
& VAS_EBOOT_CS5536_MSR_GL_REGION_BASE_MASK)
| VAS_EBOOT_CS5536_MSR_GL_REGION_IO
| VAS_EBOOT_CS5536_MSR_GL_REGION_ENABLE);
}
static inline void
set_iod (VasEBoot_pci_device_t dev, int num, int dest, int start, int mask)
{
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_GL_IOD_START + num,
((VasEBoot_uint64_t) dest << VAS_EBOOT_CS5536_IOD_DEST_SHIFT)
| (((VasEBoot_uint64_t) start & VAS_EBOOT_CS5536_IOD_ADDR_MASK)
<< VAS_EBOOT_CS5536_IOD_BASE_SHIFT)
| ((mask & VAS_EBOOT_CS5536_IOD_ADDR_MASK)
<< VAS_EBOOT_CS5536_IOD_MASK_SHIFT));
}
static inline void
set_p2d (VasEBoot_pci_device_t dev, int num, int dest, VasEBoot_uint32_t start)
{
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_GL_P2D_START + num,
(((VasEBoot_uint64_t) dest) << VAS_EBOOT_CS5536_P2D_DEST_SHIFT)
| ((VasEBoot_uint64_t) (start >> VAS_EBOOT_CS5536_P2D_LOG_ALIGN)
<< VAS_EBOOT_CS5536_P2D_BASE_SHIFT)
| (((1 << (32 - VAS_EBOOT_CS5536_P2D_LOG_ALIGN)) - 1)
<< VAS_EBOOT_CS5536_P2D_MASK_SHIFT));
}
void
VasEBoot_cs5536_init_geode (VasEBoot_pci_device_t dev)
{
/* Enable more BARs. */
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_IRQ_MAP_BAR,
VAS_EBOOT_CS5536_LBAR_TURN_ON | VAS_EBOOT_CS5536_LBAR_IRQ_MAP);
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_MFGPT_BAR,
VAS_EBOOT_CS5536_LBAR_TURN_ON | VAS_EBOOT_CS5536_LBAR_MFGPT);
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_ACPI_BAR,
VAS_EBOOT_CS5536_LBAR_TURN_ON | VAS_EBOOT_CS5536_LBAR_ACPI);
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_PM_BAR,
VAS_EBOOT_CS5536_LBAR_TURN_ON | VAS_EBOOT_CS5536_LBAR_PM);
/* Setup DIVIL. */
#ifdef VAS_EBOOT_MACHINE_MIPS_LOONGSON
switch (VasEBoot_arch_machine)
{
case VAS_EBOOT_ARCH_MACHINE_YEELOONG:
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO,
VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_MODE_X86
| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_F_REMAP
| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_RTC_ENABLE0
| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_RTC_ENABLE1);
break;
case VAS_EBOOT_ARCH_MACHINE_FULOONG2F:
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO,
VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_UART2_COM3
| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_UART1_COM1
| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_MODE_X86
| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_F_REMAP
| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_RTC_ENABLE0
| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_RTC_ENABLE1);
break;
}
#endif
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_DIVIL_IRQ_MAPPER_PRIMARY_MASK,
(~VAS_EBOOT_CS5536_DIVIL_LPC_INTERRUPTS) & 0xffff);
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_DIVIL_IRQ_MAPPER_LPC_MASK,
VAS_EBOOT_CS5536_DIVIL_LPC_INTERRUPTS);
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_DIVIL_LPC_SERIAL_IRQ_CONTROL,
VAS_EBOOT_CS5536_MSR_DIVIL_LPC_SERIAL_IRQ_CONTROL_ENABLE);
/* Initialise USB controller. */
/* FIXME: assign adresses dynamically. */
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_USB_OHCI_BASE,
VAS_EBOOT_CS5536_MSR_USB_BASE_BUS_MASTER
| VAS_EBOOT_CS5536_MSR_USB_BASE_MEMORY_ENABLE
| 0x05024000);
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_USB_EHCI_BASE,
VAS_EBOOT_CS5536_MSR_USB_BASE_BUS_MASTER
| VAS_EBOOT_CS5536_MSR_USB_BASE_MEMORY_ENABLE
| (0x20ULL << VAS_EBOOT_CS5536_MSR_USB_EHCI_BASE_FLDJ_SHIFT)
| 0x05023000);
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_USB_CONTROLLER_BASE,
VAS_EBOOT_CS5536_MSR_USB_BASE_BUS_MASTER
| VAS_EBOOT_CS5536_MSR_USB_BASE_MEMORY_ENABLE | 0x05020000);
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_USB_OPTION_CONTROLLER_BASE,
VAS_EBOOT_CS5536_MSR_USB_BASE_MEMORY_ENABLE | 0x05022000);
set_p2d (dev, 0, VAS_EBOOT_CS5536_DESTINATION_USB, 0x05020000);
set_p2d (dev, 1, VAS_EBOOT_CS5536_DESTINATION_USB, 0x05022000);
set_p2d (dev, 5, VAS_EBOOT_CS5536_DESTINATION_USB, 0x05024000);
set_p2d (dev, 6, VAS_EBOOT_CS5536_DESTINATION_USB, 0x05023000);
{
volatile VasEBoot_uint32_t *oc;
oc = VasEBoot_absolute_pointer (VasEBoot_pci_device_map_range (dev, 0x05022000,
VAS_EBOOT_CS5536_USB_OPTION_REGS_SIZE));
oc[VAS_EBOOT_CS5536_USB_OPTION_REG_UOCMUX] =
(oc[VAS_EBOOT_CS5536_USB_OPTION_REG_UOCMUX]
& ~VAS_EBOOT_CS5536_USB_OPTION_REG_UOCMUX_PMUX_MASK)
| VAS_EBOOT_CS5536_USB_OPTION_REG_UOCMUX_PMUX_HC;
VasEBoot_pci_device_unmap_range (dev, oc, VAS_EBOOT_CS5536_USB_OPTION_REGS_SIZE);
}
/* Setup IDE controller. */
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_IDE_IO_BAR,
VAS_EBOOT_CS5536_LBAR_IDE
| VAS_EBOOT_CS5536_MSR_IDE_IO_BAR_UNITS);
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_IDE_CFG,
VAS_EBOOT_CS5536_MSR_IDE_CFG_CHANNEL_ENABLE);
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_IDE_TIMING,
(VAS_EBOOT_CS5536_MSR_IDE_TIMING_PIO0
<< VAS_EBOOT_CS5536_MSR_IDE_TIMING_DRIVE0_SHIFT)
| (VAS_EBOOT_CS5536_MSR_IDE_TIMING_PIO0
<< VAS_EBOOT_CS5536_MSR_IDE_TIMING_DRIVE1_SHIFT));
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING,
(VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_CMD_PIO0
<< VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_CMD_SHIFT)
| (VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_PIO0
<< VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_DRIVE0_SHIFT)
| (VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_PIO0
<< VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_DRIVE1_SHIFT));
/* Setup Geodelink PCI. */
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL,
(4ULL << VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL_OUT_THR_SHIFT)
| (4ULL << VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL_IN_THR_SHIFT)
| (8ULL << VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL_LATENCY_SHIFT)
| VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL_IO_ENABLE
| VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL_MEMORY_ENABLE);
/* Setup windows. */
set_io_space (dev, 0, VAS_EBOOT_CS5536_LBAR_SMBUS, VAS_EBOOT_CS5536_SMBUS_REGS_SIZE);
set_io_space (dev, 1, VAS_EBOOT_CS5536_LBAR_GPIO, VAS_EBOOT_CS5536_GPIO_REGS_SIZE);
set_io_space (dev, 2, VAS_EBOOT_CS5536_LBAR_MFGPT, VAS_EBOOT_CS5536_MFGPT_REGS_SIZE);
set_io_space (dev, 3, VAS_EBOOT_CS5536_LBAR_IRQ_MAP, VAS_EBOOT_CS5536_IRQ_MAP_REGS_SIZE);
set_io_space (dev, 4, VAS_EBOOT_CS5536_LBAR_PM, VAS_EBOOT_CS5536_PM_REGS_SIZE);
set_io_space (dev, 5, VAS_EBOOT_CS5536_LBAR_ACPI, VAS_EBOOT_CS5536_ACPI_REGS_SIZE);
set_iod (dev, 0, VAS_EBOOT_CS5536_DESTINATION_IDE, VAS_EBOOT_ATA_CH0_PORT1, 0xffff8);
set_iod (dev, 1, VAS_EBOOT_CS5536_DESTINATION_ACC, VAS_EBOOT_CS5536_LBAR_ACC, 0xfff80);
set_iod (dev, 2, VAS_EBOOT_CS5536_DESTINATION_IDE, VAS_EBOOT_CS5536_LBAR_IDE, 0xffff0);
}