460 lines
16 KiB
C
460 lines
16 KiB
C
/*
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* VAS_EBOOT -- GRand Unified Bootloader
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* Copyright (C) 2005,2006,2007,2008,2009,2010 Free Software Foundation, Inc.
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*
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* VAS_EBOOT is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* VAS_EBOOT is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with VAS_EBOOT. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define VasEBoot_video_render_target VasEBoot_video_fbrender_target
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#include <VasEBoot/err.h>
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#include <VasEBoot/types.h>
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#include <VasEBoot/dl.h>
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#include <VasEBoot/misc.h>
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#include <VasEBoot/mm.h>
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#include <VasEBoot/video.h>
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#include <VasEBoot/video_fb.h>
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#include <VasEBoot/pci.h>
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#include <VasEBoot/vga.h>
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#include <VasEBoot/cache.h>
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#define VAS_EBOOT_SIS315PRO_PCIID 0x03251039
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#define VAS_EBOOT_SIS315PRO_TOTAL_MEMORY_SPACE 0x800000
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#define VAS_EBOOT_SIS315PRO_MMIO_SPACE 0x1000
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static struct
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{
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struct VasEBoot_video_mode_info mode_info;
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VasEBoot_uint8_t *ptr;
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volatile VasEBoot_uint8_t *direct_ptr;
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int mapped;
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VasEBoot_uint32_t base;
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VasEBoot_uint32_t mmiobase;
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volatile VasEBoot_uint32_t *mmioptr;
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VasEBoot_pci_device_t dev;
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VasEBoot_port_t io;
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} framebuffer;
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static VasEBoot_uint8_t
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read_sis_cmd (VasEBoot_uint8_t addr)
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{
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VasEBoot_outb (addr, framebuffer.io + 0x44);
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return VasEBoot_inb (framebuffer.io + 0x45);
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}
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static void
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write_sis_cmd (VasEBoot_uint8_t val, VasEBoot_uint8_t addr)
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{
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VasEBoot_outb (addr, framebuffer.io + 0x44);
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VasEBoot_outb (val, framebuffer.io + 0x45);
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}
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#ifndef TEST
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static VasEBoot_err_t
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VasEBoot_video_sis315pro_video_init (void)
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{
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/* Reset frame buffer. */
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VasEBoot_memset (&framebuffer, 0, sizeof(framebuffer));
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return VasEBoot_video_fb_init ();
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}
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static VasEBoot_err_t
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VasEBoot_video_sis315pro_video_fini (void)
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{
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if (framebuffer.mapped)
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{
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VasEBoot_pci_device_unmap_range (framebuffer.dev, framebuffer.ptr,
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VAS_EBOOT_SIS315PRO_TOTAL_MEMORY_SPACE);
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VasEBoot_pci_device_unmap_range (framebuffer.dev, framebuffer.direct_ptr,
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VAS_EBOOT_SIS315PRO_TOTAL_MEMORY_SPACE);
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}
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return VasEBoot_video_fb_fini ();
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}
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#endif
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#include "sis315_init.c"
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#ifndef TEST
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/* Helper for VasEBoot_video_sis315pro_setup. */
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static int
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find_card (VasEBoot_pci_device_t dev, VasEBoot_pci_id_t pciid, void *data)
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{
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int *found = data;
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VasEBoot_pci_address_t addr;
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VasEBoot_uint32_t class;
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addr = VasEBoot_pci_make_address (dev, VAS_EBOOT_PCI_REG_CLASS);
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class = VasEBoot_pci_read (addr);
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if (((class >> 16) & 0xffff) != VAS_EBOOT_PCI_CLASS_DISPLAY_VGA
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|| pciid != VAS_EBOOT_SIS315PRO_PCIID)
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return 0;
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*found = 1;
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addr = VasEBoot_pci_make_address (dev, VAS_EBOOT_PCI_REG_ADDRESS_REG0);
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framebuffer.base = VasEBoot_pci_read (addr) & VAS_EBOOT_PCI_ADDR_MEM_MASK;
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addr = VasEBoot_pci_make_address (dev, VAS_EBOOT_PCI_REG_ADDRESS_REG1);
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framebuffer.mmiobase = VasEBoot_pci_read (addr) & VAS_EBOOT_PCI_ADDR_MEM_MASK;
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addr = VasEBoot_pci_make_address (dev, VAS_EBOOT_PCI_REG_ADDRESS_REG2);
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framebuffer.io = (VasEBoot_pci_read (addr) & VAS_EBOOT_PCI_ADDR_IO_MASK)
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+ VAS_EBOOT_MACHINE_PCI_IO_BASE;
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framebuffer.dev = dev;
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return 1;
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}
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#endif
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static VasEBoot_err_t
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VasEBoot_video_sis315pro_setup (unsigned int width, unsigned int height,
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unsigned int mode_type,
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unsigned int mode_mask __attribute__ ((unused)))
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{
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int depth;
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VasEBoot_err_t err;
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int found = 0;
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unsigned i;
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#ifndef TEST
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/* Decode depth from mode_type. If it is zero, then autodetect. */
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depth = (mode_type & VAS_EBOOT_VIDEO_MODE_TYPE_DEPTH_MASK)
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>> VAS_EBOOT_VIDEO_MODE_TYPE_DEPTH_POS;
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if ((width != 640 && width != 0) || (height != 480 && height != 0)
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|| (depth != 8 && depth != 0))
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return VasEBoot_error (VAS_EBOOT_ERR_NOT_IMPLEMENTED_YET,
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"Only 640x480x8 is supported");
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VasEBoot_pci_iterate (find_card, &found);
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if (!found)
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return VasEBoot_error (VAS_EBOOT_ERR_IO, "Couldn't find graphics card");
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#endif
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/* Fill mode info details. */
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framebuffer.mode_info.width = 640;
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framebuffer.mode_info.height = 480;
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framebuffer.mode_info.mode_type = (VAS_EBOOT_VIDEO_MODE_TYPE_INDEX_COLOR
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| VAS_EBOOT_VIDEO_MODE_TYPE_DOUBLE_BUFFERED
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| VAS_EBOOT_VIDEO_MODE_TYPE_UPDATING_SWAP);
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framebuffer.mode_info.bpp = 8;
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framebuffer.mode_info.bytes_per_pixel = 1;
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framebuffer.mode_info.pitch = 640 * 1;
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framebuffer.mode_info.number_of_colors = 16;
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framebuffer.mode_info.red_mask_size = 0;
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framebuffer.mode_info.red_field_pos = 0;
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framebuffer.mode_info.green_mask_size = 0;
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framebuffer.mode_info.green_field_pos = 0;
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framebuffer.mode_info.blue_mask_size = 0;
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framebuffer.mode_info.blue_field_pos = 0;
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framebuffer.mode_info.reserved_mask_size = 0;
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framebuffer.mode_info.reserved_field_pos = 0;
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#ifndef TEST
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framebuffer.mode_info.blit_format
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= VasEBoot_video_get_blit_format (&framebuffer.mode_info);
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#endif
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#ifndef TEST
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if (found && (framebuffer.base == 0 || framebuffer.mmiobase == 0))
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{
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VasEBoot_pci_address_t addr;
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/* FIXME: choose address dynamically if needed. */
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framebuffer.base = 0x40000000;
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framebuffer.mmiobase = 0x04000000;
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framebuffer.io = 0xb300;
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addr = VasEBoot_pci_make_address (framebuffer.dev, VAS_EBOOT_PCI_REG_ADDRESS_REG0);
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VasEBoot_pci_write (addr, framebuffer.base | VAS_EBOOT_PCI_ADDR_MEM_PREFETCH);
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addr = VasEBoot_pci_make_address (framebuffer.dev, VAS_EBOOT_PCI_REG_ADDRESS_REG1);
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VasEBoot_pci_write (addr, framebuffer.mmiobase);
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addr = VasEBoot_pci_make_address (framebuffer.dev, VAS_EBOOT_PCI_REG_ADDRESS_REG2);
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VasEBoot_pci_write (addr, framebuffer.io | VAS_EBOOT_PCI_ADDR_SPACE_IO);
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/* Set latency. */
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addr = VasEBoot_pci_make_address (framebuffer.dev, VAS_EBOOT_PCI_REG_CACHELINE);
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VasEBoot_pci_write (addr, 0x80004700);
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/* Enable address spaces. */
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addr = VasEBoot_pci_make_address (framebuffer.dev, VAS_EBOOT_PCI_REG_COMMAND);
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VasEBoot_pci_write (addr, 0x7);
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addr = VasEBoot_pci_make_address (framebuffer.dev, 0x30);
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VasEBoot_pci_write (addr, 0x04060001);
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framebuffer.io += VAS_EBOOT_MACHINE_PCI_IO_BASE;
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}
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#endif
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/* We can safely discard volatile attribute. */
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#ifndef TEST
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framebuffer.ptr
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= VasEBoot_pci_device_map_range_cached (framebuffer.dev,
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framebuffer.base,
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VAS_EBOOT_SIS315PRO_TOTAL_MEMORY_SPACE);
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framebuffer.direct_ptr
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= VasEBoot_pci_device_map_range (framebuffer.dev,
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framebuffer.base,
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VAS_EBOOT_SIS315PRO_TOTAL_MEMORY_SPACE);
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framebuffer.mmioptr = VasEBoot_pci_device_map_range (framebuffer.dev,
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framebuffer.mmiobase,
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VAS_EBOOT_SIS315PRO_MMIO_SPACE);
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#endif
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framebuffer.mapped = 1;
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#ifndef TEST
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/* Prevent garbage from appearing on the screen. */
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VasEBoot_memset (framebuffer.ptr, 0,
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framebuffer.mode_info.height * framebuffer.mode_info.pitch);
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VasEBoot_arch_sync_dma_caches (framebuffer.ptr,
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framebuffer.mode_info.height
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* framebuffer.mode_info.pitch);
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#endif
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VasEBoot_outb (VAS_EBOOT_VGA_IO_MISC_NEGATIVE_VERT_POLARITY
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| VAS_EBOOT_VGA_IO_MISC_NEGATIVE_HORIZ_POLARITY
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| VAS_EBOOT_VGA_IO_MISC_UPPER_64K
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| VAS_EBOOT_VGA_IO_MISC_EXTERNAL_CLOCK_0
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| VAS_EBOOT_VGA_IO_MISC_28MHZ
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| VAS_EBOOT_VGA_IO_MISC_ENABLE_VRAM_ACCESS
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| VAS_EBOOT_VGA_IO_MISC_COLOR,
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VAS_EBOOT_VGA_IO_MISC_WRITE + VAS_EBOOT_MACHINE_PCI_IO_BASE);
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VasEBoot_vga_sr_write (0x86, 5);
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for (i = 6; i <= 0x27; i++)
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VasEBoot_vga_sr_write (0, i);
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for (i = 0x31; i <= 0x3d; i++)
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VasEBoot_vga_sr_write (0, i);
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for (i = 0; i < ARRAY_SIZE (sr_dump); i++)
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VasEBoot_vga_sr_write (sr_dump[i].val, sr_dump[i].reg);
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for (i = 0x30; i < 0x40; i++)
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VasEBoot_vga_cr_write (0, i);
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VasEBoot_vga_cr_write (0x77, 0x40);
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VasEBoot_vga_cr_write (0x77, 0x41);
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VasEBoot_vga_cr_write (0x00, 0x42);
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VasEBoot_vga_cr_write (0x5b, 0x43);
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VasEBoot_vga_cr_write (0x00, 0x44);
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VasEBoot_vga_cr_write (0x23, 0x48);
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VasEBoot_vga_cr_write (0xaa, 0x49);
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VasEBoot_vga_cr_write (0x02, 0x37);
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VasEBoot_vga_cr_write (0x20, 0x5b);
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VasEBoot_vga_cr_write (0x00, 0x83);
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VasEBoot_vga_cr_write (0x80, 0x63);
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VasEBoot_vga_cr_write (0x0c, VAS_EBOOT_VGA_CR_VSYNC_END);
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VasEBoot_vga_cr_write (0x5f, VAS_EBOOT_VGA_CR_HTOTAL);
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VasEBoot_vga_cr_write (0x4f, VAS_EBOOT_VGA_CR_HORIZ_END);
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VasEBoot_vga_cr_write (0x50, VAS_EBOOT_VGA_CR_HBLANK_START);
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VasEBoot_vga_cr_write (0x82, VAS_EBOOT_VGA_CR_HBLANK_END);
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VasEBoot_vga_cr_write (0x54, VAS_EBOOT_VGA_CR_HORIZ_SYNC_PULSE_START);
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VasEBoot_vga_cr_write (0x80, VAS_EBOOT_VGA_CR_HORIZ_SYNC_PULSE_END);
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VasEBoot_vga_cr_write (0x0b, VAS_EBOOT_VGA_CR_VERT_TOTAL);
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VasEBoot_vga_cr_write (0x3e, VAS_EBOOT_VGA_CR_OVERFLOW);
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VasEBoot_vga_cr_write (0x00, VAS_EBOOT_VGA_CR_BYTE_PANNING);
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VasEBoot_vga_cr_write (0x40, VAS_EBOOT_VGA_CR_CELL_HEIGHT);
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VasEBoot_vga_cr_write (0x00, VAS_EBOOT_VGA_CR_CURSOR_START);
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VasEBoot_vga_cr_write (0x00, VAS_EBOOT_VGA_CR_CURSOR_END);
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VasEBoot_vga_cr_write (0x00, VAS_EBOOT_VGA_CR_START_ADDR_HIGH_REGISTER);
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VasEBoot_vga_cr_write (0x00, VAS_EBOOT_VGA_CR_START_ADDR_LOW_REGISTER);
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VasEBoot_vga_cr_write (0x00, VAS_EBOOT_VGA_CR_CURSOR_ADDR_HIGH);
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VasEBoot_vga_cr_write (0x00, VAS_EBOOT_VGA_CR_CURSOR_ADDR_LOW);
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VasEBoot_vga_cr_write (0xea, VAS_EBOOT_VGA_CR_VSYNC_START);
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VasEBoot_vga_cr_write (0x8c, VAS_EBOOT_VGA_CR_VSYNC_END);
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VasEBoot_vga_cr_write (0xdf, VAS_EBOOT_VGA_CR_VDISPLAY_END);
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VasEBoot_vga_cr_write (0x28, VAS_EBOOT_VGA_CR_PITCH);
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VasEBoot_vga_cr_write (0x40, VAS_EBOOT_VGA_CR_UNDERLINE_LOCATION);
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VasEBoot_vga_cr_write (0xe7, VAS_EBOOT_VGA_CR_VERTICAL_BLANK_START);
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VasEBoot_vga_cr_write (0x04, VAS_EBOOT_VGA_CR_VERTICAL_BLANK_END);
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VasEBoot_vga_cr_write (0xa3, VAS_EBOOT_VGA_CR_MODE);
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VasEBoot_vga_cr_write (0xff, VAS_EBOOT_VGA_CR_LINE_COMPARE);
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VasEBoot_vga_cr_write (0x0c, VAS_EBOOT_VGA_CR_VSYNC_END);
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VasEBoot_vga_cr_write (0x5f, VAS_EBOOT_VGA_CR_HTOTAL);
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VasEBoot_vga_cr_write (0x4f, VAS_EBOOT_VGA_CR_HORIZ_END);
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VasEBoot_vga_cr_write (0x50, VAS_EBOOT_VGA_CR_HBLANK_START);
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VasEBoot_vga_cr_write (0x82, VAS_EBOOT_VGA_CR_HBLANK_END);
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VasEBoot_vga_cr_write (0x55, VAS_EBOOT_VGA_CR_HORIZ_SYNC_PULSE_START);
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VasEBoot_vga_cr_write (0x81, VAS_EBOOT_VGA_CR_HORIZ_SYNC_PULSE_END);
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VasEBoot_vga_cr_write (0x0b, VAS_EBOOT_VGA_CR_VERT_TOTAL);
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VasEBoot_vga_cr_write (0x3e, VAS_EBOOT_VGA_CR_OVERFLOW);
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VasEBoot_vga_cr_write (0xe9, VAS_EBOOT_VGA_CR_VSYNC_START);
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VasEBoot_vga_cr_write (0x8b, VAS_EBOOT_VGA_CR_VSYNC_END);
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VasEBoot_vga_cr_write (0xdf, VAS_EBOOT_VGA_CR_VDISPLAY_END);
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VasEBoot_vga_cr_write (0xe7, VAS_EBOOT_VGA_CR_VERTICAL_BLANK_START);
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VasEBoot_vga_cr_write (0x04, VAS_EBOOT_VGA_CR_VERTICAL_BLANK_END);
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VasEBoot_vga_cr_write (0x40, VAS_EBOOT_VGA_CR_CELL_HEIGHT);
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VasEBoot_vga_cr_write (0x50, VAS_EBOOT_VGA_CR_PITCH);
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VasEBoot_vga_cr_write (0x00, 0x19);
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VasEBoot_vga_cr_write (0x00, 0x1a);
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VasEBoot_vga_cr_write (0x6c, 0x52);
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VasEBoot_vga_cr_write (0x2e, 0x34);
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VasEBoot_vga_cr_write (0x00, 0x31);
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VasEBoot_vga_cr_write (0, VAS_EBOOT_VGA_CR_START_ADDR_HIGH_REGISTER);
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VasEBoot_vga_cr_write (0, VAS_EBOOT_VGA_CR_START_ADDR_LOW_REGISTER);
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for (i = 0; i < 16; i++)
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VasEBoot_vga_write_arx (i, i);
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VasEBoot_vga_write_arx (1, VAS_EBOOT_VGA_ARX_MODE);
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VasEBoot_vga_write_arx (0, VAS_EBOOT_VGA_ARX_OVERSCAN);
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VasEBoot_vga_write_arx (0, VAS_EBOOT_VGA_ARX_COLOR_PLANE_ENABLE);
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VasEBoot_vga_write_arx (0, VAS_EBOOT_VGA_ARX_HORIZONTAL_PANNING);
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VasEBoot_vga_write_arx (0, VAS_EBOOT_VGA_ARX_COLOR_SELECT);
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VasEBoot_outb (0xff, VAS_EBOOT_VGA_IO_PIXEL_MASK + VAS_EBOOT_MACHINE_PCI_IO_BASE);
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for (i = 0; i < ARRAY_SIZE (gr); i++)
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VasEBoot_vga_gr_write (gr[i], i);
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for (i = 0; i < VAS_EBOOT_VIDEO_FBSTD_NUMCOLORS; i++)
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VasEBoot_vga_palette_write (i, VasEBoot_video_fbstd_colors[i].r,
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VasEBoot_video_fbstd_colors[i].g,
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VasEBoot_video_fbstd_colors[i].b);
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#if 1
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{
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if (read_sis_cmd (0x5) != 0xa1)
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write_sis_cmd (0x86, 0x5);
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write_sis_cmd (read_sis_cmd (0x20) | 0xa1, 0x20);
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write_sis_cmd (read_sis_cmd (0x1e) | 0xda, 0x1e);
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#define IND_SIS_CMDQUEUE_SET 0x26
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#define IND_SIS_CMDQUEUE_THRESHOLD 0x27
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#define COMMAND_QUEUE_THRESHOLD 0x1F
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#define SIS_CMD_QUEUE_RESET 0x01
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#define SIS_AGP_CMDQUEUE_ENABLE 0x80 /* 315/330/340 series SR26 */
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#define SIS_VRAM_CMDQUEUE_ENABLE 0x40
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#define SIS_MMIO_CMD_ENABLE 0x20
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#define SIS_CMD_QUEUE_SIZE_512k 0x00
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#define SIS_CMD_QUEUE_SIZE_1M 0x04
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#define SIS_CMD_QUEUE_SIZE_2M 0x08
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#define SIS_CMD_QUEUE_SIZE_4M 0x0C
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#define SIS_CMD_QUEUE_RESET 0x01
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#define SIS_CMD_AUTO_CORR 0x02
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write_sis_cmd (COMMAND_QUEUE_THRESHOLD, IND_SIS_CMDQUEUE_THRESHOLD);
|
|
write_sis_cmd (SIS_CMD_QUEUE_RESET, IND_SIS_CMDQUEUE_SET);
|
|
framebuffer.mmioptr[0x85C4 / 4] = framebuffer.mmioptr[0x85C8 / 4];
|
|
write_sis_cmd (SIS_MMIO_CMD_ENABLE | SIS_CMD_AUTO_CORR, IND_SIS_CMDQUEUE_SET);
|
|
framebuffer.mmioptr[0x85C0 / 4] = (0x1000000 - (512 * 1024));
|
|
}
|
|
#endif
|
|
|
|
#ifndef TEST
|
|
err = VasEBoot_video_fb_setup (mode_type, mode_mask,
|
|
&framebuffer.mode_info,
|
|
framebuffer.ptr, NULL, NULL);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Copy default palette to initialize emulated palette. */
|
|
err = VasEBoot_video_fb_set_palette (0, VAS_EBOOT_VIDEO_FBSTD_EXT_NUMCOLORS,
|
|
VasEBoot_video_fbstd_colors);
|
|
#endif
|
|
return err;
|
|
}
|
|
|
|
#ifndef TEST
|
|
|
|
static VasEBoot_err_t
|
|
VasEBoot_video_sis315pro_swap_buffers (void)
|
|
{
|
|
VasEBoot_size_t s;
|
|
s = (framebuffer.mode_info.height
|
|
* framebuffer.mode_info.pitch
|
|
* framebuffer.mode_info.bytes_per_pixel);
|
|
VasEBoot_video_fb_swap_buffers ();
|
|
VasEBoot_arch_sync_dma_caches (framebuffer.ptr, s);
|
|
return VAS_EBOOT_ERR_NONE;
|
|
}
|
|
|
|
static VasEBoot_err_t
|
|
VasEBoot_video_sis315pro_get_info_and_fini (struct VasEBoot_video_mode_info *mode_info,
|
|
void **framebuf)
|
|
{
|
|
VasEBoot_memcpy (mode_info, &(framebuffer.mode_info), sizeof (*mode_info));
|
|
*framebuf = (void *) framebuffer.direct_ptr;
|
|
|
|
VasEBoot_video_fb_fini ();
|
|
|
|
return VAS_EBOOT_ERR_NONE;
|
|
}
|
|
|
|
static struct VasEBoot_video_adapter VasEBoot_video_sis315pro_adapter =
|
|
{
|
|
.name = "SIS315PRO Video Driver",
|
|
.id = VAS_EBOOT_VIDEO_DRIVER_SIS315PRO,
|
|
|
|
.prio = VAS_EBOOT_VIDEO_ADAPTER_PRIO_NATIVE,
|
|
|
|
.init = VasEBoot_video_sis315pro_video_init,
|
|
.fini = VasEBoot_video_sis315pro_video_fini,
|
|
.setup = VasEBoot_video_sis315pro_setup,
|
|
.get_info = VasEBoot_video_fb_get_info,
|
|
.get_info_and_fini = VasEBoot_video_sis315pro_get_info_and_fini,
|
|
.set_palette = VasEBoot_video_fb_set_palette,
|
|
.get_palette = VasEBoot_video_fb_get_palette,
|
|
.set_viewport = VasEBoot_video_fb_set_viewport,
|
|
.get_viewport = VasEBoot_video_fb_get_viewport,
|
|
.set_region = VasEBoot_video_fb_set_region,
|
|
.get_region = VasEBoot_video_fb_get_region,
|
|
.set_area_status = VasEBoot_video_fb_set_area_status,
|
|
.get_area_status = VasEBoot_video_fb_get_area_status,
|
|
.map_color = VasEBoot_video_fb_map_color,
|
|
.map_rgb = VasEBoot_video_fb_map_rgb,
|
|
.map_rgba = VasEBoot_video_fb_map_rgba,
|
|
.unmap_color = VasEBoot_video_fb_unmap_color,
|
|
.fill_rect = VasEBoot_video_fb_fill_rect,
|
|
.blit_bitmap = VasEBoot_video_fb_blit_bitmap,
|
|
.blit_render_target = VasEBoot_video_fb_blit_render_target,
|
|
.scroll = VasEBoot_video_fb_scroll,
|
|
.swap_buffers = VasEBoot_video_sis315pro_swap_buffers,
|
|
.create_render_target = VasEBoot_video_fb_create_render_target,
|
|
.delete_render_target = VasEBoot_video_fb_delete_render_target,
|
|
.set_active_render_target = VasEBoot_video_fb_set_active_render_target,
|
|
.get_active_render_target = VasEBoot_video_fb_get_active_render_target,
|
|
|
|
.next = 0
|
|
};
|
|
|
|
VAS_EBOOT_MOD_INIT(video_sis315pro)
|
|
{
|
|
VasEBoot_video_register (&VasEBoot_video_sis315pro_adapter);
|
|
}
|
|
|
|
VAS_EBOOT_MOD_FINI(video_sis315pro)
|
|
{
|
|
VasEBoot_video_unregister (&VasEBoot_video_sis315pro_adapter);
|
|
}
|
|
#else
|
|
int
|
|
main ()
|
|
{
|
|
VasEBoot_video_sis315pro_setup (640, 400, 0, 0);
|
|
}
|
|
#endif
|