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vaseboot/VasEBoot-core/video/sm712.c

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/*
* VasEBoot -- GRand Unified Bootloader
* Copyright (C) 2005,2006,2007,2008,2009,2010 Free Software Foundation, Inc.
*
* VasEBoot is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* VasEBoot is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with VasEBoot. If not, see <http://www.gnu.org/licenses/>.
*/
#define VasEBoot_video_render_target VasEBoot_video_fbrender_target
#if !defined (TEST) && !defined(GENINIT)
#include <VasEBoot/err.h>
#include <VasEBoot/types.h>
#include <VasEBoot/dl.h>
#include <VasEBoot/misc.h>
#include <VasEBoot/mm.h>
#include <VasEBoot/video.h>
#include <VasEBoot/video_fb.h>
#include <VasEBoot/pci.h>
#include <VasEBoot/vga.h>
#include <VasEBoot/cache.h>
#else
typedef unsigned char VasEBoot_uint8_t;
typedef unsigned short VasEBoot_uint16_t;
typedef unsigned int VasEBoot_uint32_t;
typedef int VasEBoot_err_t;
#include <VasEBoot/vgaregs.h>
#include <stdio.h>
#define ARRAY_SIZE(array) (sizeof (array) / sizeof (array[0]))
#endif
#include "sm712_init.c"
#pragma GCC diagnostic ignored "-Wcast-align"
#define VasEBoot_SM712_TOTAL_MEMORY_SPACE 0x700400
#define VasEBoot_SM712_REG_BASE 0x700000
#define VasEBoot_SM712_PCIID 0x0712126f
enum
{
VasEBoot_SM712_SR_TV_CONTROL = 0x65,
VasEBoot_SM712_SR_RAM_LUT = 0x66,
VasEBoot_SM712_SR_CLOCK_CONTROL1 = 0x68,
VasEBoot_SM712_SR_CLOCK_CONTROL2 = 0x69,
VasEBoot_SM712_SR_VCLK_NUM = 0x6c,
VasEBoot_SM712_SR_VCLK_DENOM = 0x6d,
VasEBoot_SM712_SR_VCLK2_NUM = 0x6e,
VasEBoot_SM712_SR_VCLK2_DENOM = 0x6f,
VasEBoot_SM712_SR_POPUP_ICON_LOW = 0x80,
VasEBoot_SM712_SR_POPUP_ICON_HIGH = 0x81,
VasEBoot_SM712_SR_POPUP_ICON_CTRL = 0x82,
VasEBoot_SM712_SR_POPUP_ICON_COLOR1 = 0x84,
VasEBoot_SM712_SR_POPUP_ICON_COLOR2 = 0x85,
VasEBoot_SM712_SR_POPUP_ICON_COLOR3 = 0x86,
VasEBoot_SM712_SR_HW_CURSOR_UPPER_LEFT_X_LOW = 0x88,
VasEBoot_SM712_SR_HW_CURSOR_UPPER_LEFT_X_HIGH = 0x89,
VasEBoot_SM712_SR_HW_CURSOR_UPPER_LEFT_Y_LOW = 0x8a,
VasEBoot_SM712_SR_HW_CURSOR_UPPER_LEFT_Y_HIGH = 0x8b,
VasEBoot_SM712_SR_HW_CURSOR_FG_COLOR = 0x8c,
VasEBoot_SM712_SR_HW_CURSOR_BG_COLOR = 0x8d,
VasEBoot_SM712_SR_POPUP_ICON_X_LOW = 0x90,
VasEBoot_SM712_SR_POPUP_ICON_X_HIGH = 0x91,
VasEBoot_SM712_SR_POPUP_ICON_Y_LOW = 0x92,
VasEBoot_SM712_SR_POPUP_ICON_Y_HIGH = 0x93,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_CONTROL = 0xa0,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_COLOR_KEY_LOW = 0xa1,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_COLOR_KEY_HIGH = 0xa2,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_COLOR_KEY_MASK_LOW = 0xa3,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_COLOR_KEY_MASK_HIGH = 0xa4,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_RED_CONSTANT = 0xa5,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_GREEN_CONSTANT = 0xa6,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_BLUE_CONSTANT = 0xa7,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_TOP_BOUNDARY = 0xa8,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_LEFT_BOUNDARY = 0xa9,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_BOTTOM_BOUNDARY = 0xaa,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_RIGHT_BOUNDARY = 0xab,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_TOP_LEFT_OVERFLOW_BOUNDARY = 0xac,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_BOTTOM_RIGHT_OVERFLOW_BOUNDARY = 0xad,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_VERTICAL_STRETCH_FACTOR = 0xae,
VasEBoot_SM712_SR_PANEL_HW_VIDEO_HORIZONTAL_STRETCH_FACTOR = 0xaf,
};
enum
{
VasEBoot_SM712_SR_TV_CRT_SRAM = 0x00,
VasEBoot_SM712_SR_TV_LCD_SRAM = 0x08
};
enum
{
VasEBoot_SM712_SR_TV_ALT_CLOCK = 0x00,
VasEBoot_SM712_SR_TV_FREE_RUN_CLOCK = 0x04
};
enum
{
VasEBoot_SM712_SR_TV_CLOCK_CKIN_NTSC = 0x00,
VasEBoot_SM712_SR_TV_CLOCK_REFCLK_PAL = 0x04
};
enum
{
VasEBoot_SM712_SR_TV_HSYNC = 0x00,
VasEBoot_SM712_SR_TV_COMPOSITE_HSYNC = 0x01
};
enum
{
VasEBoot_SM712_SR_RAM_LUT_NORMAL = 0,
VasEBoot_SM712_SR_RAM_LUT_LCD_RAM_OFF = 0x80,
VasEBoot_SM712_SR_RAM_LUT_CRT_RAM_OFF = 0x40,
VasEBoot_SM712_SR_RAM_LUT_LCD_RAM_NO_WRITE = 0x20,
VasEBoot_SM712_SR_RAM_LUT_CRT_RAM_NO_WRITE = 0x10,
VasEBoot_SM712_SR_RAM_LUT_CRT_8BIT = 0x08,
VasEBoot_SM712_SR_RAM_LUT_CRT_GAMMA = 0x04
};
enum
{
VasEBoot_SM712_SR_CLOCK_CONTROL1_VCLK_FROM_CCR = 0x40,
VasEBoot_SM712_SR_CLOCK_CONTROL1_8DOT_CLOCK = 0x10,
};
enum
{
VasEBoot_SM712_SR_CLOCK_CONTROL2_PROGRAM_VCLOCK = 0x03
};
#define VasEBoot_SM712_SR_POPUP_ICON_HIGH_MASK 0x7
#define VasEBoot_SM712_SR_POPUP_ICON_HIGH_HW_CURSOR_EN 0x80
enum
{
VasEBoot_SM712_SR_POPUP_ICON_CTRL_DISABLED = 0,
VasEBoot_SM712_SR_POPUP_ICON_CTRL_ZOOM_ENABLED = 0x40,
VasEBoot_SM712_SR_POPUP_ICON_CTRL_ENABLED = 0x80
};
#define RGB332_BLACK 0
#define RGB332_WHITE 0xff
enum
{
VasEBoot_SM712_CR_OVERFLOW_INTERLACE = 0x30,
VasEBoot_SM712_CR_INTERLACE_RETRACE = 0x31,
VasEBoot_SM712_CR_TV_VDISPLAY_START = 0x32,
VasEBoot_SM712_CR_TV_VDISPLAY_END_HIGH = 0x33,
VasEBoot_SM712_CR_TV_VDISPLAY_END_LOW = 0x34,
VasEBoot_SM712_CR_DDA_CONTROL_LOW = 0x35,
VasEBoot_SM712_CR_DDA_CONTROL_HIGH = 0x36,
VasEBoot_SM712_CR_TV_EQUALIZER = 0x38,
VasEBoot_SM712_CR_TV_SERRATION = 0x39,
VasEBoot_SM712_CR_HSYNC_CTRL = 0x3a,
VasEBoot_SM712_CR_DEBUG = 0x3c,
VasEBoot_SM712_CR_SHADOW_VGA_HTOTAL = 0x40,
VasEBoot_SM712_CR_SHADOW_VGA_HBLANK_START = 0x41,
VasEBoot_SM712_CR_SHADOW_VGA_HBLANK_END = 0x42,
VasEBoot_SM712_CR_SHADOW_VGA_HRETRACE_START = 0x43,
VasEBoot_SM712_CR_SHADOW_VGA_HRETRACE_END = 0x44,
VasEBoot_SM712_CR_SHADOW_VGA_VERTICAL_TOTAL = 0x45,
VasEBoot_SM712_CR_SHADOW_VGA_VBLANK_START = 0x46,
VasEBoot_SM712_CR_SHADOW_VGA_VBLANK_END = 0x47,
VasEBoot_SM712_CR_SHADOW_VGA_VRETRACE_START = 0x48,
VasEBoot_SM712_CR_SHADOW_VGA_VRETRACE_END = 0x49,
VasEBoot_SM712_CR_SHADOW_VGA_OVERFLOW = 0x4a,
VasEBoot_SM712_CR_SHADOW_VGA_CELL_HEIGHT = 0x4b,
VasEBoot_SM712_CR_SHADOW_VGA_HDISPLAY_END = 0x4c,
VasEBoot_SM712_CR_SHADOW_VGA_VDISPLAY_END = 0x4d,
VasEBoot_SM712_CR_DDA_LOOKUP_REG3_START = 0x90,
VasEBoot_SM712_CR_DDA_LOOKUP_REG2_START = 0x91,
VasEBoot_SM712_CR_DDA_LOOKUP_REG1_START = 0xa0,
VasEBoot_SM712_CR_VCENTERING_OFFSET = 0xa6,
VasEBoot_SM712_CR_HCENTERING_OFFSET = 0xa7,
};
#define VasEBoot_SM712_CR_DEBUG_NONE 0
#define SM712_DDA_REG3_COMPARE_SHIFT 2
#define SM712_DDA_REG3_COMPARE_MASK 0xfc
#define SM712_DDA_REG3_DDA_SHIFT 8
#define SM712_DDA_REG3_DDA_MASK 0x3
#define SM712_DDA_REG2_DDA_MASK 0xff
#define SM712_DDA_REG2_VCENTER_MASK 0x3f
static struct
{
VasEBoot_uint8_t compare;
VasEBoot_uint16_t dda;
VasEBoot_uint8_t vcentering;
} dda_lookups[] = {
{ 21, 469, 2},
{ 23, 477, 2},
{ 33, 535, 2},
{ 35, 682, 21},
{ 34, 675, 2},
{ 55, 683, 6},
};
static struct
{
#if !defined (TEST) && !defined(GENINIT)
struct VasEBoot_video_mode_info mode_info;
#endif
volatile VasEBoot_uint8_t *ptr;
VasEBoot_uint8_t *cached_ptr;
int mapped;
VasEBoot_uint32_t base;
#if !defined (TEST) && !defined(GENINIT)
VasEBoot_pci_device_t dev;
#endif
} framebuffer;
#if !defined (TEST) && !defined(GENINIT)
static VasEBoot_err_t
VasEBoot_video_sm712_video_init (void)
{
/* Reset frame buffer. */
VasEBoot_memset (&framebuffer, 0, sizeof(framebuffer));
return VasEBoot_video_fb_init ();
}
static VasEBoot_err_t
VasEBoot_video_sm712_video_fini (void)
{
if (framebuffer.mapped)
{
VasEBoot_pci_device_unmap_range (framebuffer.dev, framebuffer.ptr,
VasEBoot_SM712_TOTAL_MEMORY_SPACE);
VasEBoot_pci_device_unmap_range (framebuffer.dev, framebuffer.cached_ptr,
VasEBoot_SM712_TOTAL_MEMORY_SPACE);
}
return VasEBoot_video_fb_fini ();
}
#endif
static inline void
VasEBoot_sm712_write_reg (VasEBoot_uint8_t val, VasEBoot_uint16_t addr)
{
#ifdef TEST
printf (" {1, 0x%x, 0x%x},\n", addr, val);
#elif defined (GENINIT)
printf (" .byte 0x%02x, 0x%02x\n", (addr - 0x3c0), val);
if ((addr - 0x3c0) & ~0x7f)
printf ("FAIL\n");
#else
*(volatile VasEBoot_uint8_t *) (framebuffer.ptr + VasEBoot_SM712_REG_BASE
+ addr) = val;
#endif
}
static inline VasEBoot_uint8_t
VasEBoot_sm712_read_reg (VasEBoot_uint16_t addr)
{
#ifdef TEST
printf (" {-1, 0x%x, 0x5},\n", addr);
#elif defined (GENINIT)
if ((addr - 0x3c0) & ~0x7f)
printf ("FAIL\n");
printf (" .byte 0x%04x, 0x00\n", (addr - 0x3c0) | 0x80);
#else
return *(volatile VasEBoot_uint8_t *) (framebuffer.ptr + VasEBoot_SM712_REG_BASE
+ addr);
#endif
}
static inline VasEBoot_uint8_t
VasEBoot_sm712_sr_read (VasEBoot_uint8_t addr)
{
VasEBoot_sm712_write_reg (addr, VasEBoot_VGA_IO_SR_INDEX);
return VasEBoot_sm712_read_reg (VasEBoot_VGA_IO_SR_DATA);
}
static inline void
VasEBoot_sm712_sr_write (VasEBoot_uint8_t val, VasEBoot_uint8_t addr)
{
VasEBoot_sm712_write_reg (addr, VasEBoot_VGA_IO_SR_INDEX);
VasEBoot_sm712_write_reg (val, VasEBoot_VGA_IO_SR_DATA);
}
static inline void
VasEBoot_sm712_gr_write (VasEBoot_uint8_t val, VasEBoot_uint8_t addr)
{
VasEBoot_sm712_write_reg (addr, VasEBoot_VGA_IO_GR_INDEX);
VasEBoot_sm712_write_reg (val, VasEBoot_VGA_IO_GR_DATA);
}
static inline void
VasEBoot_sm712_cr_write (VasEBoot_uint8_t val, VasEBoot_uint8_t addr)
{
VasEBoot_sm712_write_reg (addr, VasEBoot_VGA_IO_CR_INDEX);
VasEBoot_sm712_write_reg (val, VasEBoot_VGA_IO_CR_DATA);
}
static inline void
VasEBoot_sm712_write_arx (VasEBoot_uint8_t val, VasEBoot_uint8_t addr)
{
VasEBoot_sm712_read_reg (VasEBoot_VGA_IO_INPUT_STATUS1_REGISTER);
VasEBoot_sm712_write_reg (addr, VasEBoot_VGA_IO_ARX);
VasEBoot_sm712_read_reg (VasEBoot_VGA_IO_ARX_READ);
VasEBoot_sm712_write_reg (val, VasEBoot_VGA_IO_ARX);
}
static inline void
VasEBoot_sm712_cr_shadow_write (VasEBoot_uint8_t val, VasEBoot_uint8_t addr)
{
VasEBoot_uint8_t mapping[] =
{
[VasEBoot_VGA_CR_HTOTAL] = VasEBoot_SM712_CR_SHADOW_VGA_HTOTAL,
[VasEBoot_VGA_CR_HORIZ_END] = 0xff,
[VasEBoot_VGA_CR_HBLANK_START] = VasEBoot_SM712_CR_SHADOW_VGA_HBLANK_START,
[VasEBoot_VGA_CR_HBLANK_END] = VasEBoot_SM712_CR_SHADOW_VGA_HBLANK_END,
[VasEBoot_VGA_CR_HORIZ_SYNC_PULSE_START] = VasEBoot_SM712_CR_SHADOW_VGA_HRETRACE_START,
[VasEBoot_VGA_CR_HORIZ_SYNC_PULSE_END] = VasEBoot_SM712_CR_SHADOW_VGA_HRETRACE_END,
[VasEBoot_VGA_CR_VERT_TOTAL] = VasEBoot_SM712_CR_SHADOW_VGA_VERTICAL_TOTAL,
[VasEBoot_VGA_CR_OVERFLOW] = VasEBoot_SM712_CR_SHADOW_VGA_OVERFLOW,
[VasEBoot_VGA_CR_BYTE_PANNING] = 0xff,
[VasEBoot_VGA_CR_CELL_HEIGHT] = VasEBoot_SM712_CR_SHADOW_VGA_CELL_HEIGHT,
[VasEBoot_VGA_CR_CURSOR_START] = 0xff,
[VasEBoot_VGA_CR_CURSOR_END] = 0xff,
[VasEBoot_VGA_CR_START_ADDR_HIGH_REGISTER] = 0xff,
[VasEBoot_VGA_CR_START_ADDR_LOW_REGISTER] = 0xff,
[VasEBoot_VGA_CR_CURSOR_ADDR_HIGH] = 0xff,
[VasEBoot_VGA_CR_CURSOR_ADDR_LOW] = 0xff,
[VasEBoot_VGA_CR_VSYNC_START] = VasEBoot_SM712_CR_SHADOW_VGA_VRETRACE_START,
[VasEBoot_VGA_CR_VSYNC_END] = VasEBoot_SM712_CR_SHADOW_VGA_VRETRACE_END,
[VasEBoot_VGA_CR_VDISPLAY_END] = VasEBoot_SM712_CR_SHADOW_VGA_VDISPLAY_END,
[VasEBoot_VGA_CR_PITCH] = VasEBoot_SM712_CR_SHADOW_VGA_HDISPLAY_END,
[VasEBoot_VGA_CR_UNDERLINE_LOCATION] = 0xff,
[VasEBoot_VGA_CR_VERTICAL_BLANK_START] = VasEBoot_SM712_CR_SHADOW_VGA_VBLANK_START,
[VasEBoot_VGA_CR_VERTICAL_BLANK_END] = VasEBoot_SM712_CR_SHADOW_VGA_VBLANK_END,
[VasEBoot_VGA_CR_MODE] = 0xff,
[VasEBoot_VGA_CR_LINE_COMPARE] = 0xff
};
if (addr >= ARRAY_SIZE (mapping) || mapping[addr] == 0xff)
return;
VasEBoot_sm712_cr_write (val, mapping[addr]);
}
static inline void
VasEBoot_sm712_write_dda_lookup (int idx, VasEBoot_uint8_t compare, VasEBoot_uint16_t dda,
VasEBoot_uint8_t vcentering)
{
VasEBoot_sm712_cr_write (((compare << SM712_DDA_REG3_COMPARE_SHIFT)
& SM712_DDA_REG3_COMPARE_MASK)
| ((dda >> SM712_DDA_REG3_DDA_SHIFT)
& SM712_DDA_REG3_DDA_MASK),
VasEBoot_SM712_CR_DDA_LOOKUP_REG3_START + 2 * idx);
VasEBoot_sm712_cr_write (dda & SM712_DDA_REG2_DDA_MASK,
VasEBoot_SM712_CR_DDA_LOOKUP_REG2_START + 2 * idx);
VasEBoot_sm712_cr_write (vcentering & SM712_DDA_REG2_VCENTER_MASK,
VasEBoot_SM712_CR_DDA_LOOKUP_REG1_START + idx);
}
#if !defined (TEST) && !defined(GENINIT)
/* Helper for VasEBoot_video_sm712_setup. */
static int
find_card (VasEBoot_pci_device_t dev, VasEBoot_pci_id_t pciid, void *data)
{
int *found = data;
VasEBoot_pci_address_t addr;
VasEBoot_uint32_t class;
addr = VasEBoot_pci_make_address (dev, VasEBoot_PCI_REG_CLASS);
class = VasEBoot_pci_read (addr);
if (((class >> 16) & 0xffff) != VasEBoot_PCI_CLASS_SUBCLASS_VGA
|| pciid != VasEBoot_SM712_PCIID)
return 0;
*found = 1;
addr = VasEBoot_pci_make_address (dev, VasEBoot_PCI_REG_ADDRESS_REG0);
framebuffer.base = VasEBoot_pci_read (addr);
framebuffer.dev = dev;
return 1;
}
#endif
static VasEBoot_err_t
VasEBoot_video_sm712_setup (unsigned int width, unsigned int height,
unsigned int mode_type, unsigned int mode_mask __attribute__ ((unused)))
{
unsigned i;
#if !defined (TEST) && !defined(GENINIT)
int depth;
VasEBoot_err_t err;
int found = 0;
/* Decode depth from mode_type. If it is zero, then autodetect. */
depth = (mode_type & VasEBoot_VIDEO_MODE_TYPE_DEPTH_MASK)
>> VasEBoot_VIDEO_MODE_TYPE_DEPTH_POS;
if ((width != 1024 && width != 0) || (height != 600 && height != 0)
|| (depth != 16 && depth != 0))
return VasEBoot_error (VasEBoot_ERR_NOT_IMPLEMENTED_YET,
"Only 1024x600x16 is supported");
VasEBoot_pci_iterate (find_card, &found);
if (!found)
return VasEBoot_error (VasEBoot_ERR_IO, "Couldn't find graphics card");
/* Fill mode info details. */
framebuffer.mode_info.width = 1024;
framebuffer.mode_info.height = 600;
framebuffer.mode_info.mode_type = (VasEBoot_VIDEO_MODE_TYPE_RGB
| VasEBoot_VIDEO_MODE_TYPE_DOUBLE_BUFFERED
| VasEBoot_VIDEO_MODE_TYPE_UPDATING_SWAP);
framebuffer.mode_info.bpp = 16;
framebuffer.mode_info.bytes_per_pixel = 2;
framebuffer.mode_info.pitch = 1024 * 2;
framebuffer.mode_info.number_of_colors = 256;
framebuffer.mode_info.red_mask_size = 5;
framebuffer.mode_info.red_field_pos = 11;
framebuffer.mode_info.green_mask_size = 6;
framebuffer.mode_info.green_field_pos = 5;
framebuffer.mode_info.blue_mask_size = 5;
framebuffer.mode_info.blue_field_pos = 0;
framebuffer.mode_info.reserved_mask_size = 0;
framebuffer.mode_info.reserved_field_pos = 0;
framebuffer.mode_info.blit_format
= VasEBoot_video_get_blit_format (&framebuffer.mode_info);
#endif
#if !defined (TEST) && !defined(GENINIT)
if (found && framebuffer.base == 0)
{
VasEBoot_pci_address_t addr;
/* FIXME: choose address dynamically if needed. */
framebuffer.base = 0x04000000;
addr = VasEBoot_pci_make_address (framebuffer.dev, VasEBoot_PCI_REG_ADDRESS_REG0);
VasEBoot_pci_write (addr, framebuffer.base);
/* Set latency. */
addr = VasEBoot_pci_make_address (framebuffer.dev, VasEBoot_PCI_REG_CACHELINE);
VasEBoot_pci_write (addr, 0x8);
/* Enable address spaces. */
addr = VasEBoot_pci_make_address (framebuffer.dev, VasEBoot_PCI_REG_COMMAND);
VasEBoot_pci_write (addr, 0x7);
}
#endif
/* We can safely discard volatile attribute. */
#if !defined (TEST) && !defined(GENINIT)
framebuffer.ptr
= VasEBoot_pci_device_map_range (framebuffer.dev,
framebuffer.base,
VasEBoot_SM712_TOTAL_MEMORY_SPACE);
framebuffer.cached_ptr
= VasEBoot_pci_device_map_range_cached (framebuffer.dev,
framebuffer.base,
VasEBoot_SM712_TOTAL_MEMORY_SPACE);
#endif
framebuffer.mapped = 1;
/* Initialise SM712. */
#if !defined (TEST) && !defined(GENINIT)
/* FIXME */
VasEBoot_vga_sr_write (0x11, 0x18);
#endif
#if !defined (TEST) && !defined(GENINIT)
/* Prevent garbage from appearing on the screen. */
VasEBoot_memset ((void *) framebuffer.cached_ptr, 0,
framebuffer.mode_info.height * framebuffer.mode_info.pitch);
#endif
/* FIXME */
VasEBoot_sm712_sr_write (0, 0x21);
VasEBoot_sm712_sr_write (0x7a, 0x62);
VasEBoot_sm712_sr_write (0x16, 0x6a);
VasEBoot_sm712_sr_write (0x2, 0x6b);
VasEBoot_sm712_write_reg (0, VasEBoot_VGA_IO_PIXEL_MASK);
VasEBoot_sm712_sr_write (VasEBoot_VGA_SR_RESET_ASYNC, VasEBoot_VGA_SR_RESET);
VasEBoot_sm712_write_reg (VasEBoot_VGA_IO_MISC_NEGATIVE_VERT_POLARITY
| VasEBoot_VGA_IO_MISC_NEGATIVE_HORIZ_POLARITY
| VasEBoot_VGA_IO_MISC_UPPER_64K
| VasEBoot_VGA_IO_MISC_EXTERNAL_CLOCK_0
| VasEBoot_VGA_IO_MISC_ENABLE_VRAM_ACCESS
| VasEBoot_VGA_IO_MISC_COLOR, VasEBoot_VGA_IO_MISC_WRITE);
VasEBoot_sm712_sr_write (VasEBoot_VGA_SR_RESET_ASYNC | VasEBoot_VGA_SR_RESET_SYNC,
VasEBoot_VGA_SR_RESET);
VasEBoot_sm712_sr_write (VasEBoot_VGA_SR_CLOCKING_MODE_8_DOT_CLOCK,
VasEBoot_VGA_SR_CLOCKING_MODE);
VasEBoot_sm712_sr_write (VasEBoot_VGA_ALL_PLANES, VasEBoot_VGA_SR_MAP_MASK_REGISTER);
VasEBoot_sm712_sr_write (0, VasEBoot_VGA_SR_CHAR_MAP_SELECT);
VasEBoot_sm712_sr_write (VasEBoot_VGA_SR_MEMORY_MODE_CHAIN4
| VasEBoot_VGA_SR_MEMORY_MODE_SEQUENTIAL_ADDRESSING
| VasEBoot_VGA_SR_MEMORY_MODE_EXTERNAL_VIDEO_MEMORY,
VasEBoot_VGA_SR_MEMORY_MODE);
for (i = 0; i < ARRAY_SIZE (sm712_sr_seq1); i++)
VasEBoot_sm712_sr_write (sm712_sr_seq1[i], 0x10 + i);
for (i = 0; i < ARRAY_SIZE (sm712_sr_seq2); i++)
VasEBoot_sm712_sr_write (sm712_sr_seq2[i], 0x30 + i);
/* Undocumented. */
VasEBoot_sm712_sr_write (0x1a, 0x63);
/* Undocumented. */
VasEBoot_sm712_sr_write (0x1a, 0x64);
VasEBoot_sm712_sr_write (VasEBoot_SM712_SR_TV_CRT_SRAM | VasEBoot_SM712_SR_TV_ALT_CLOCK
| VasEBoot_SM712_SR_TV_CLOCK_CKIN_NTSC
| VasEBoot_SM712_SR_TV_HSYNC,
VasEBoot_SM712_SR_TV_CONTROL);
VasEBoot_sm712_sr_write (VasEBoot_SM712_SR_RAM_LUT_NORMAL, VasEBoot_SM712_SR_RAM_LUT);
/* Undocumented. */
VasEBoot_sm712_sr_write (0x00, 0x67);
VasEBoot_sm712_sr_write (VasEBoot_SM712_SR_CLOCK_CONTROL1_VCLK_FROM_CCR
| VasEBoot_SM712_SR_CLOCK_CONTROL1_8DOT_CLOCK,
VasEBoot_SM712_SR_CLOCK_CONTROL1);
VasEBoot_sm712_sr_write (VasEBoot_SM712_SR_CLOCK_CONTROL2_PROGRAM_VCLOCK,
VasEBoot_SM712_SR_CLOCK_CONTROL2);
VasEBoot_sm712_sr_write (82, VasEBoot_SM712_SR_VCLK_NUM);
VasEBoot_sm712_sr_write (137, VasEBoot_SM712_SR_VCLK_DENOM);
VasEBoot_sm712_sr_write (9, VasEBoot_SM712_SR_VCLK2_NUM);
VasEBoot_sm712_sr_write (2, VasEBoot_SM712_SR_VCLK2_DENOM);
/* FIXME */
VasEBoot_sm712_sr_write (0x04, 0x70);
/* FIXME */
VasEBoot_sm712_sr_write (0x45, 0x71);
/* Undocumented */
VasEBoot_sm712_sr_write (0x30, 0x72);
/* Undocumented */
VasEBoot_sm712_sr_write (0x30, 0x73);
/* Undocumented */
VasEBoot_sm712_sr_write (0x40, 0x74);
/* Undocumented */
VasEBoot_sm712_sr_write (0x20, 0x75);
VasEBoot_sm712_sr_write (0xff, VasEBoot_SM712_SR_POPUP_ICON_LOW);
VasEBoot_sm712_sr_write (VasEBoot_SM712_SR_POPUP_ICON_HIGH_MASK,
VasEBoot_SM712_SR_POPUP_ICON_HIGH);
VasEBoot_sm712_sr_write (VasEBoot_SM712_SR_POPUP_ICON_CTRL_DISABLED,
VasEBoot_SM712_SR_POPUP_ICON_CTRL);
/* Undocumented */
VasEBoot_sm712_sr_write (0x0, 0x83);
VasEBoot_sm712_sr_write (8, VasEBoot_SM712_SR_POPUP_ICON_COLOR1);
VasEBoot_sm712_sr_write (0, VasEBoot_SM712_SR_POPUP_ICON_COLOR2);
VasEBoot_sm712_sr_write (0x42, VasEBoot_SM712_SR_POPUP_ICON_COLOR3);
/* Undocumented */
VasEBoot_sm712_sr_write (0x3a, 0x87);
/* Why theese coordinates? */
VasEBoot_sm712_sr_write (0x59, VasEBoot_SM712_SR_HW_CURSOR_UPPER_LEFT_X_LOW);
VasEBoot_sm712_sr_write (0x02, VasEBoot_SM712_SR_HW_CURSOR_UPPER_LEFT_X_HIGH);
VasEBoot_sm712_sr_write (0x44, VasEBoot_SM712_SR_HW_CURSOR_UPPER_LEFT_Y_LOW);
VasEBoot_sm712_sr_write (0x02, VasEBoot_SM712_SR_HW_CURSOR_UPPER_LEFT_Y_HIGH);
VasEBoot_sm712_sr_write (RGB332_BLACK, VasEBoot_SM712_SR_HW_CURSOR_FG_COLOR);
VasEBoot_sm712_sr_write (RGB332_WHITE, VasEBoot_SM712_SR_HW_CURSOR_BG_COLOR);
/* Undocumented */
VasEBoot_sm712_sr_write (0x3a, 0x8e);
VasEBoot_sm712_sr_write (0x3a, 0x8f);
VasEBoot_sm712_sr_write (0, VasEBoot_SM712_SR_POPUP_ICON_X_LOW);
VasEBoot_sm712_sr_write (0, VasEBoot_SM712_SR_POPUP_ICON_X_HIGH);
VasEBoot_sm712_sr_write (0, VasEBoot_SM712_SR_POPUP_ICON_Y_LOW);
VasEBoot_sm712_sr_write (0, VasEBoot_SM712_SR_POPUP_ICON_Y_HIGH);
VasEBoot_sm712_sr_write (0, VasEBoot_SM712_SR_PANEL_HW_VIDEO_CONTROL);
VasEBoot_sm712_sr_write (0x10, VasEBoot_SM712_SR_PANEL_HW_VIDEO_COLOR_KEY_LOW);
VasEBoot_sm712_sr_write (0x08, VasEBoot_SM712_SR_PANEL_HW_VIDEO_COLOR_KEY_HIGH);
VasEBoot_sm712_sr_write (0x00, VasEBoot_SM712_SR_PANEL_HW_VIDEO_COLOR_KEY_MASK_LOW);
VasEBoot_sm712_sr_write (0x02, VasEBoot_SM712_SR_PANEL_HW_VIDEO_COLOR_KEY_MASK_HIGH);
VasEBoot_sm712_sr_write (0xed, VasEBoot_SM712_SR_PANEL_HW_VIDEO_RED_CONSTANT);
VasEBoot_sm712_sr_write (0xed, VasEBoot_SM712_SR_PANEL_HW_VIDEO_GREEN_CONSTANT);
VasEBoot_sm712_sr_write (0xed, VasEBoot_SM712_SR_PANEL_HW_VIDEO_BLUE_CONSTANT);
VasEBoot_sm712_sr_write (0x7b, VasEBoot_SM712_SR_PANEL_HW_VIDEO_TOP_BOUNDARY);
VasEBoot_sm712_sr_write (0xfb, VasEBoot_SM712_SR_PANEL_HW_VIDEO_LEFT_BOUNDARY);
VasEBoot_sm712_sr_write (0xff, VasEBoot_SM712_SR_PANEL_HW_VIDEO_BOTTOM_BOUNDARY);
VasEBoot_sm712_sr_write (0xff, VasEBoot_SM712_SR_PANEL_HW_VIDEO_RIGHT_BOUNDARY);
/* Doesn't match documentation? */
VasEBoot_sm712_sr_write (0x97, VasEBoot_SM712_SR_PANEL_HW_VIDEO_TOP_LEFT_OVERFLOW_BOUNDARY);
VasEBoot_sm712_sr_write (0xef, VasEBoot_SM712_SR_PANEL_HW_VIDEO_BOTTOM_RIGHT_OVERFLOW_BOUNDARY);
VasEBoot_sm712_sr_write (0xbf, VasEBoot_SM712_SR_PANEL_HW_VIDEO_VERTICAL_STRETCH_FACTOR);
VasEBoot_sm712_sr_write (0xdf, VasEBoot_SM712_SR_PANEL_HW_VIDEO_HORIZONTAL_STRETCH_FACTOR);
VasEBoot_sm712_gr_write (VasEBoot_VGA_NO_PLANES, VasEBoot_VGA_GR_SET_RESET_PLANE);
VasEBoot_sm712_gr_write (VasEBoot_VGA_NO_PLANES, VasEBoot_VGA_GR_SET_RESET_PLANE_ENABLE);
VasEBoot_sm712_gr_write (VasEBoot_VGA_NO_PLANES, VasEBoot_VGA_GR_COLOR_COMPARE);
VasEBoot_sm712_gr_write (VasEBoot_VGA_GR_DATA_ROTATE_NOP, VasEBoot_VGA_GR_DATA_ROTATE);
VasEBoot_sm712_gr_write (VasEBoot_VGA_NO_PLANES, VasEBoot_VGA_GR_READ_MAP_REGISTER);
VasEBoot_sm712_gr_write (VasEBoot_VGA_GR_MODE_256_COLOR, VasEBoot_VGA_GR_MODE);
VasEBoot_sm712_gr_write (VasEBoot_VGA_GR_GR6_MMAP_A0
| VasEBoot_VGA_GR_GR6_GRAPHICS_MODE, VasEBoot_VGA_GR_GR6);
VasEBoot_sm712_gr_write (VasEBoot_VGA_ALL_PLANES, VasEBoot_VGA_GR_COLOR_COMPARE_DISABLE);
VasEBoot_sm712_gr_write (0xff, VasEBoot_VGA_GR_BITMASK);
/* Write palette mapping. */
for (i = 0; i < 16; i++)
VasEBoot_sm712_write_arx (i, i);
VasEBoot_sm712_write_arx (VasEBoot_VGA_ARX_MODE_ENABLE_256COLOR
| VasEBoot_VGA_ARX_MODE_GRAPHICS, VasEBoot_VGA_ARX_MODE);
VasEBoot_sm712_write_arx (0, VasEBoot_VGA_ARX_OVERSCAN);
VasEBoot_sm712_write_arx (VasEBoot_VGA_ALL_PLANES, VasEBoot_VGA_ARX_COLOR_PLANE_ENABLE);
VasEBoot_sm712_write_arx (0, VasEBoot_VGA_ARX_HORIZONTAL_PANNING);
VasEBoot_sm712_write_arx (0, VasEBoot_VGA_ARX_COLOR_SELECT);
/* FIXME: compute this generically. */
{
struct VasEBoot_video_hw_config config =
{
.vertical_total = 806,
.vertical_blank_start = 0x300,
.vertical_blank_end = 0,
.vertical_sync_start = 0x303,
.vertical_sync_end = 0x9,
.line_compare = 0x3ff,
.vdisplay_end = 0x300,
.pitch = 0x80,
.horizontal_total = 164,
.horizontal_end = 128,
.horizontal_blank_start = 128,
.horizontal_blank_end = 0,
.horizontal_sync_pulse_start = 133,
.horizontal_sync_pulse_end = 22
};
VasEBoot_vga_set_geometry (&config, VasEBoot_sm712_cr_write);
config.horizontal_sync_pulse_start = 134;
config.horizontal_sync_pulse_end = 21;
config.vertical_sync_start = 0x301;
config.vertical_sync_end = 0x0;
config.line_compare = 0x0ff;
config.vdisplay_end = 0x258;
config.pitch = 0x7f;
VasEBoot_vga_set_geometry (&config, VasEBoot_sm712_cr_shadow_write);
}
VasEBoot_sm712_cr_write (VasEBoot_VGA_CR_BYTE_PANNING_NORMAL,
VasEBoot_VGA_CR_BYTE_PANNING);
VasEBoot_sm712_cr_write (0, VasEBoot_VGA_CR_CURSOR_START);
VasEBoot_sm712_cr_write (0, VasEBoot_VGA_CR_CURSOR_END);
VasEBoot_sm712_cr_write (0, VasEBoot_VGA_CR_START_ADDR_HIGH_REGISTER);
VasEBoot_sm712_cr_write (0, VasEBoot_VGA_CR_START_ADDR_LOW_REGISTER);
VasEBoot_sm712_cr_write (0, VasEBoot_VGA_CR_CURSOR_ADDR_HIGH);
VasEBoot_sm712_cr_write (0, VasEBoot_VGA_CR_CURSOR_ADDR_LOW);
VasEBoot_sm712_cr_write (VasEBoot_VGA_CR_UNDERLINE_LOCATION_DWORD_MODE,
VasEBoot_VGA_CR_UNDERLINE_LOCATION);
VasEBoot_sm712_cr_write (VasEBoot_VGA_CR_MODE_ADDRESS_WRAP
| VasEBoot_VGA_CR_MODE_BYTE_MODE
| VasEBoot_VGA_CR_MODE_TIMING_ENABLE
| VasEBoot_VGA_CR_MODE_NO_CGA
| VasEBoot_VGA_CR_MODE_NO_HERCULES,
VasEBoot_VGA_CR_MODE);
VasEBoot_sm712_cr_write (0, VasEBoot_SM712_CR_OVERFLOW_INTERLACE);
VasEBoot_sm712_cr_write (0, VasEBoot_SM712_CR_INTERLACE_RETRACE);
VasEBoot_sm712_cr_write (0, VasEBoot_SM712_CR_TV_VDISPLAY_START);
VasEBoot_sm712_cr_write (0, VasEBoot_SM712_CR_TV_VDISPLAY_END_HIGH);
VasEBoot_sm712_cr_write (0, VasEBoot_SM712_CR_TV_VDISPLAY_END_LOW);
VasEBoot_sm712_cr_write (0x80, VasEBoot_SM712_CR_DDA_CONTROL_LOW);
VasEBoot_sm712_cr_write (0x02, VasEBoot_SM712_CR_DDA_CONTROL_HIGH);
/* Undocumented */
VasEBoot_sm712_cr_write (0x20, 0x37);
VasEBoot_sm712_cr_write (0, VasEBoot_SM712_CR_TV_EQUALIZER);
VasEBoot_sm712_cr_write (0, VasEBoot_SM712_CR_TV_SERRATION);
VasEBoot_sm712_cr_write (0, VasEBoot_SM712_CR_HSYNC_CTRL);
/* Undocumented */
VasEBoot_sm712_cr_write (0x40, 0x3b);
VasEBoot_sm712_cr_write (VasEBoot_SM712_CR_DEBUG_NONE, VasEBoot_SM712_CR_DEBUG);
/* Undocumented */
VasEBoot_sm712_cr_write (0xff, 0x3d);
VasEBoot_sm712_cr_write (0x46, 0x3e);
VasEBoot_sm712_cr_write (0x91, 0x3f);
for (i = 0; i < ARRAY_SIZE (dda_lookups); i++)
VasEBoot_sm712_write_dda_lookup (i, dda_lookups[i].compare, dda_lookups[i].dda,
dda_lookups[i].vcentering);
/* Undocumented */
VasEBoot_sm712_cr_write (0, 0x9c);
VasEBoot_sm712_cr_write (0, 0x9d);
VasEBoot_sm712_cr_write (0, 0x9e);
VasEBoot_sm712_cr_write (0, 0x9f);
VasEBoot_sm712_cr_write (0, VasEBoot_SM712_CR_VCENTERING_OFFSET);
VasEBoot_sm712_cr_write (0, VasEBoot_SM712_CR_HCENTERING_OFFSET);
VasEBoot_sm712_write_reg (VasEBoot_VGA_IO_MISC_NEGATIVE_HORIZ_POLARITY
| VasEBoot_VGA_IO_MISC_UPPER_64K
| VasEBoot_VGA_IO_MISC_28MHZ
| VasEBoot_VGA_IO_MISC_ENABLE_VRAM_ACCESS
| VasEBoot_VGA_IO_MISC_COLOR,
VasEBoot_VGA_IO_MISC_WRITE);
#if !defined (TEST) && !defined(GENINIT)
/* Undocumented? */
*(volatile VasEBoot_uint32_t *) ((char *) framebuffer.ptr + 0x40c00c) = 0;
*(volatile VasEBoot_uint32_t *) ((char *) framebuffer.ptr + 0x40c040) = 0;
*(volatile VasEBoot_uint32_t *) ((char *) framebuffer.ptr + 0x40c000) = 0x20000;
*(volatile VasEBoot_uint32_t *) ((char *) framebuffer.ptr + 0x40c010) = 0x1020100;
#endif
(void) VasEBoot_sm712_sr_read (0x16);
#if !defined (TEST) && !defined(GENINIT)
err = VasEBoot_video_fb_setup (mode_type, mode_mask,
&framebuffer.mode_info,
framebuffer.cached_ptr, NULL, NULL);
if (err)
return err;
/* Copy default palette to initialize emulated palette. */
err = VasEBoot_video_fb_set_palette (0, VasEBoot_VIDEO_FBSTD_NUMCOLORS,
VasEBoot_video_fbstd_colors);
return err;
#else
return 0;
#endif
}
#if !defined (TEST) && !defined(GENINIT)
static VasEBoot_err_t
VasEBoot_video_sm712_swap_buffers (void)
{
VasEBoot_size_t s;
s = (framebuffer.mode_info.height
* framebuffer.mode_info.pitch
* framebuffer.mode_info.bytes_per_pixel);
VasEBoot_video_fb_swap_buffers ();
VasEBoot_arch_sync_dma_caches (framebuffer.cached_ptr, s);
return VasEBoot_ERR_NONE;
}
static VasEBoot_err_t
VasEBoot_video_sm712_get_info_and_fini (struct VasEBoot_video_mode_info *mode_info,
void **framebuf)
{
VasEBoot_memcpy (mode_info, &(framebuffer.mode_info), sizeof (*mode_info));
*framebuf = (char *) framebuffer.ptr;
VasEBoot_video_fb_fini ();
return VasEBoot_ERR_NONE;
}
static struct VasEBoot_video_adapter VasEBoot_video_sm712_adapter =
{
.name = "SM712 Video Driver",
.id = VasEBoot_VIDEO_DRIVER_SM712,
.prio = VasEBoot_VIDEO_ADAPTER_PRIO_NATIVE,
.init = VasEBoot_video_sm712_video_init,
.fini = VasEBoot_video_sm712_video_fini,
.setup = VasEBoot_video_sm712_setup,
.get_info = VasEBoot_video_fb_get_info,
.get_info_and_fini = VasEBoot_video_sm712_get_info_and_fini,
.set_palette = VasEBoot_video_fb_set_palette,
.get_palette = VasEBoot_video_fb_get_palette,
.set_viewport = VasEBoot_video_fb_set_viewport,
.get_viewport = VasEBoot_video_fb_get_viewport,
.set_region = VasEBoot_video_fb_set_region,
.get_region = VasEBoot_video_fb_get_region,
.set_area_status = VasEBoot_video_fb_set_area_status,
.get_area_status = VasEBoot_video_fb_get_area_status,
.map_color = VasEBoot_video_fb_map_color,
.map_rgb = VasEBoot_video_fb_map_rgb,
.map_rgba = VasEBoot_video_fb_map_rgba,
.unmap_color = VasEBoot_video_fb_unmap_color,
.fill_rect = VasEBoot_video_fb_fill_rect,
.blit_bitmap = VasEBoot_video_fb_blit_bitmap,
.blit_render_target = VasEBoot_video_fb_blit_render_target,
.scroll = VasEBoot_video_fb_scroll,
.swap_buffers = VasEBoot_video_sm712_swap_buffers,
.create_render_target = VasEBoot_video_fb_create_render_target,
.delete_render_target = VasEBoot_video_fb_delete_render_target,
.set_active_render_target = VasEBoot_video_fb_set_active_render_target,
.get_active_render_target = VasEBoot_video_fb_get_active_render_target,
.next = 0
};
VasEBoot_MOD_INIT(video_sm712)
{
VasEBoot_video_register (&VasEBoot_video_sm712_adapter);
}
VasEBoot_MOD_FINI(video_sm712)
{
VasEBoot_video_unregister (&VasEBoot_video_sm712_adapter);
}
#else
int
main ()
{
VasEBoot_video_sm712_setup (1024, 600, 0, 0);
}
#endif
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