383 lines
14 KiB
C
383 lines
14 KiB
C
/*
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* VAS_EBOOT -- GRand Unified Bootloader
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* Copyright (C) 2010 Free Software Foundation, Inc.
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*
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* VAS_EBOOT is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* VAS_EBOOT is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with VAS_EBOOT. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <VasEBoot/types.h>
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#include <VasEBoot/cs5536.h>
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#include <VasEBoot/pci.h>
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#include <VasEBoot/time.h>
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#include <VasEBoot/ata.h>
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#ifdef VAS_EBOOT_MACHINE_MIPS_LOONGSON
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#include <VasEBoot/machine/kernel.h>
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#endif
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#include <VasEBoot/dl.h>
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VAS_EBOOT_MOD_LICENSE ("GPLv3+");
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/* Context for VasEBoot_cs5536_find. */
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struct VasEBoot_cs5536_find_ctx
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{
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VasEBoot_pci_device_t *devp;
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int found;
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};
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/* Helper for VasEBoot_cs5536_find. */
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static int
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VasEBoot_cs5536_find_iter (VasEBoot_pci_device_t dev, VasEBoot_pci_id_t pciid, void *data)
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{
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struct VasEBoot_cs5536_find_ctx *ctx = data;
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if (pciid == VAS_EBOOT_CS5536_PCIID)
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{
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*ctx->devp = dev;
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ctx->found = 1;
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return 1;
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}
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return 0;
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}
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int
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VasEBoot_cs5536_find (VasEBoot_pci_device_t *devp)
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{
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struct VasEBoot_cs5536_find_ctx ctx = {
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.devp = devp,
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.found = 0
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};
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VasEBoot_pci_iterate (VasEBoot_cs5536_find_iter, &ctx);
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return ctx.found;
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}
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VasEBoot_uint64_t
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VasEBoot_cs5536_read_msr (VasEBoot_pci_device_t dev, VasEBoot_uint32_t addr)
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{
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VasEBoot_uint64_t ret = 0;
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VasEBoot_pci_write (VasEBoot_pci_make_address (dev, VAS_EBOOT_CS5536_MSR_MAILBOX_ADDR),
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addr);
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ret = (VasEBoot_uint64_t)
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VasEBoot_pci_read (VasEBoot_pci_make_address (dev, VAS_EBOOT_CS5536_MSR_MAILBOX_DATA0));
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ret |= (((VasEBoot_uint64_t)
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VasEBoot_pci_read (VasEBoot_pci_make_address (dev,
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VAS_EBOOT_CS5536_MSR_MAILBOX_DATA1)))
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<< 32);
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return ret;
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}
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void
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VasEBoot_cs5536_write_msr (VasEBoot_pci_device_t dev, VasEBoot_uint32_t addr,
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VasEBoot_uint64_t val)
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{
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VasEBoot_pci_write (VasEBoot_pci_make_address (dev, VAS_EBOOT_CS5536_MSR_MAILBOX_ADDR),
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addr);
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VasEBoot_pci_write (VasEBoot_pci_make_address (dev, VAS_EBOOT_CS5536_MSR_MAILBOX_DATA0),
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val & 0xffffffff);
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VasEBoot_pci_write (VasEBoot_pci_make_address (dev, VAS_EBOOT_CS5536_MSR_MAILBOX_DATA1),
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val >> 32);
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}
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VasEBoot_err_t
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VasEBoot_cs5536_smbus_wait (VasEBoot_port_t smbbase)
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{
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VasEBoot_uint64_t start = VasEBoot_get_time_ms ();
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while (1)
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{
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VasEBoot_uint8_t status;
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status = VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_STATUS);
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if (status & VAS_EBOOT_CS5536_SMB_REG_STATUS_SDAST)
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return VAS_EBOOT_ERR_NONE;
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if (status & VAS_EBOOT_CS5536_SMB_REG_STATUS_BER)
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return VasEBoot_error (VAS_EBOOT_ERR_IO, "SM bus error");
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if (status & VAS_EBOOT_CS5536_SMB_REG_STATUS_NACK)
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return VasEBoot_error (VAS_EBOOT_ERR_IO, "NACK received");
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if (VasEBoot_get_time_ms () > start + 40)
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return VasEBoot_error (VAS_EBOOT_ERR_IO, "SM stalled");
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}
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}
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VasEBoot_err_t
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VasEBoot_cs5536_read_spd_byte (VasEBoot_port_t smbbase, VasEBoot_uint8_t dev,
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VasEBoot_uint8_t addr, VasEBoot_uint8_t *res)
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{
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VasEBoot_err_t err;
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/* Send START. */
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VasEBoot_outb (VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1)
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| VAS_EBOOT_CS5536_SMB_REG_CTRL1_START,
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smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1);
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/* Send device address. */
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err = VasEBoot_cs5536_smbus_wait (smbbase);
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if (err)
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return err;
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VasEBoot_outb (dev << 1, smbbase + VAS_EBOOT_CS5536_SMB_REG_DATA);
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/* Send ACK. */
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err = VasEBoot_cs5536_smbus_wait (smbbase);
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if (err)
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return err;
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VasEBoot_outb (VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1)
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| VAS_EBOOT_CS5536_SMB_REG_CTRL1_ACK,
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smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1);
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/* Send byte address. */
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VasEBoot_outb (addr, smbbase + VAS_EBOOT_CS5536_SMB_REG_DATA);
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/* Send START. */
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err = VasEBoot_cs5536_smbus_wait (smbbase);
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if (err)
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return err;
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VasEBoot_outb (VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1)
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| VAS_EBOOT_CS5536_SMB_REG_CTRL1_START,
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smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1);
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/* Send device address. */
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err = VasEBoot_cs5536_smbus_wait (smbbase);
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if (err)
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return err;
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VasEBoot_outb ((dev << 1) | 1, smbbase + VAS_EBOOT_CS5536_SMB_REG_DATA);
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/* Send STOP. */
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err = VasEBoot_cs5536_smbus_wait (smbbase);
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if (err)
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return err;
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VasEBoot_outb (VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1)
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| VAS_EBOOT_CS5536_SMB_REG_CTRL1_STOP,
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smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1);
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err = VasEBoot_cs5536_smbus_wait (smbbase);
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if (err)
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return err;
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*res = VasEBoot_inb (smbbase + VAS_EBOOT_CS5536_SMB_REG_DATA);
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return VAS_EBOOT_ERR_NONE;
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}
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VasEBoot_err_t
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VasEBoot_cs5536_init_smbus (VasEBoot_pci_device_t dev, VasEBoot_uint16_t divisor,
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VasEBoot_port_t *smbbase)
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{
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VasEBoot_uint64_t smbbar;
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smbbar = VasEBoot_cs5536_read_msr (dev, VAS_EBOOT_CS5536_MSR_SMB_BAR);
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/* FIXME */
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if (!(smbbar & VAS_EBOOT_CS5536_LBAR_ENABLE))
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return VasEBoot_error(VAS_EBOOT_ERR_IO, "SMB controller not enabled\n");
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*smbbase = (smbbar & VAS_EBOOT_CS5536_LBAR_ADDR_MASK) + VAS_EBOOT_MACHINE_PCI_IO_BASE;
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if (divisor < 8)
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return VasEBoot_error (VAS_EBOOT_ERR_BAD_ARGUMENT, "invalid divisor");
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/* Disable SMB. */
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VasEBoot_outb (0, *smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL2);
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/* Disable interrupts. */
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VasEBoot_outb (0, *smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL1);
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/* Set as master. */
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VasEBoot_outb (VAS_EBOOT_CS5536_SMB_REG_ADDR_MASTER,
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*smbbase + VAS_EBOOT_CS5536_SMB_REG_ADDR);
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/* Launch. */
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VasEBoot_outb (((divisor >> 7) & 0xff), *smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL3);
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VasEBoot_outb (((divisor << 1) & 0xfe) | VAS_EBOOT_CS5536_SMB_REG_CTRL2_ENABLE,
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*smbbase + VAS_EBOOT_CS5536_SMB_REG_CTRL2);
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return VAS_EBOOT_ERR_NONE;
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}
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VasEBoot_err_t
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VasEBoot_cs5536_read_spd (VasEBoot_port_t smbbase, VasEBoot_uint8_t dev,
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struct VasEBoot_smbus_spd *res)
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{
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VasEBoot_err_t err;
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VasEBoot_size_t size;
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VasEBoot_uint8_t b;
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VasEBoot_size_t ptr;
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err = VasEBoot_cs5536_read_spd_byte (smbbase, dev, 0, &b);
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if (err)
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return err;
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if (b == 0)
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return VasEBoot_error (VAS_EBOOT_ERR_IO, "no SPD found");
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size = b;
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((VasEBoot_uint8_t *) res)[0] = b;
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for (ptr = 1; ptr < size; ptr++)
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{
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err = VasEBoot_cs5536_read_spd_byte (smbbase, dev, ptr,
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&((VasEBoot_uint8_t *) res)[ptr]);
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if (err)
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return err;
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}
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return VAS_EBOOT_ERR_NONE;
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}
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static inline void
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set_io_space (VasEBoot_pci_device_t dev, int num, VasEBoot_uint16_t start,
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VasEBoot_uint16_t len)
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{
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_GL_REGIONS_START + num,
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((((VasEBoot_uint64_t) start + len - 4)
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<< VAS_EBOOT_CS5536_MSR_GL_REGION_IO_TOP_SHIFT)
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& VAS_EBOOT_CS5536_MSR_GL_REGION_TOP_MASK)
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| (((VasEBoot_uint64_t) start
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<< VAS_EBOOT_CS5536_MSR_GL_REGION_IO_BASE_SHIFT)
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& VAS_EBOOT_CS5536_MSR_GL_REGION_BASE_MASK)
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| VAS_EBOOT_CS5536_MSR_GL_REGION_IO
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| VAS_EBOOT_CS5536_MSR_GL_REGION_ENABLE);
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}
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static inline void
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set_iod (VasEBoot_pci_device_t dev, int num, int dest, int start, int mask)
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{
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_GL_IOD_START + num,
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((VasEBoot_uint64_t) dest << VAS_EBOOT_CS5536_IOD_DEST_SHIFT)
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| (((VasEBoot_uint64_t) start & VAS_EBOOT_CS5536_IOD_ADDR_MASK)
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<< VAS_EBOOT_CS5536_IOD_BASE_SHIFT)
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| ((mask & VAS_EBOOT_CS5536_IOD_ADDR_MASK)
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<< VAS_EBOOT_CS5536_IOD_MASK_SHIFT));
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}
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static inline void
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set_p2d (VasEBoot_pci_device_t dev, int num, int dest, VasEBoot_uint32_t start)
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{
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_GL_P2D_START + num,
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(((VasEBoot_uint64_t) dest) << VAS_EBOOT_CS5536_P2D_DEST_SHIFT)
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| ((VasEBoot_uint64_t) (start >> VAS_EBOOT_CS5536_P2D_LOG_ALIGN)
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<< VAS_EBOOT_CS5536_P2D_BASE_SHIFT)
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| (((1 << (32 - VAS_EBOOT_CS5536_P2D_LOG_ALIGN)) - 1)
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<< VAS_EBOOT_CS5536_P2D_MASK_SHIFT));
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}
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void
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VasEBoot_cs5536_init_geode (VasEBoot_pci_device_t dev)
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{
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/* Enable more BARs. */
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_IRQ_MAP_BAR,
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VAS_EBOOT_CS5536_LBAR_TURN_ON | VAS_EBOOT_CS5536_LBAR_IRQ_MAP);
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_MFGPT_BAR,
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VAS_EBOOT_CS5536_LBAR_TURN_ON | VAS_EBOOT_CS5536_LBAR_MFGPT);
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_ACPI_BAR,
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VAS_EBOOT_CS5536_LBAR_TURN_ON | VAS_EBOOT_CS5536_LBAR_ACPI);
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_PM_BAR,
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VAS_EBOOT_CS5536_LBAR_TURN_ON | VAS_EBOOT_CS5536_LBAR_PM);
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/* Setup DIVIL. */
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#ifdef VAS_EBOOT_MACHINE_MIPS_LOONGSON
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switch (VasEBoot_arch_machine)
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{
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case VAS_EBOOT_ARCH_MACHINE_YEELOONG:
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO,
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VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_MODE_X86
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| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_F_REMAP
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| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_RTC_ENABLE0
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| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_RTC_ENABLE1);
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break;
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case VAS_EBOOT_ARCH_MACHINE_FULOONG2F:
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO,
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VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_UART2_COM3
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| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_UART1_COM1
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| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_MODE_X86
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| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_F_REMAP
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| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_RTC_ENABLE0
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| VAS_EBOOT_CS5536_MSR_DIVIL_LEG_IO_RTC_ENABLE1);
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break;
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}
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#endif
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_DIVIL_IRQ_MAPPER_PRIMARY_MASK,
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(~VAS_EBOOT_CS5536_DIVIL_LPC_INTERRUPTS) & 0xffff);
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_DIVIL_IRQ_MAPPER_LPC_MASK,
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VAS_EBOOT_CS5536_DIVIL_LPC_INTERRUPTS);
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_DIVIL_LPC_SERIAL_IRQ_CONTROL,
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VAS_EBOOT_CS5536_MSR_DIVIL_LPC_SERIAL_IRQ_CONTROL_ENABLE);
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/* Initialise USB controller. */
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/* FIXME: assign adresses dynamically. */
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_USB_OHCI_BASE,
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VAS_EBOOT_CS5536_MSR_USB_BASE_BUS_MASTER
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| VAS_EBOOT_CS5536_MSR_USB_BASE_MEMORY_ENABLE
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| 0x05024000);
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_USB_EHCI_BASE,
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VAS_EBOOT_CS5536_MSR_USB_BASE_BUS_MASTER
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| VAS_EBOOT_CS5536_MSR_USB_BASE_MEMORY_ENABLE
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| (0x20ULL << VAS_EBOOT_CS5536_MSR_USB_EHCI_BASE_FLDJ_SHIFT)
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| 0x05023000);
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_USB_CONTROLLER_BASE,
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VAS_EBOOT_CS5536_MSR_USB_BASE_BUS_MASTER
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| VAS_EBOOT_CS5536_MSR_USB_BASE_MEMORY_ENABLE | 0x05020000);
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_USB_OPTION_CONTROLLER_BASE,
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VAS_EBOOT_CS5536_MSR_USB_BASE_MEMORY_ENABLE | 0x05022000);
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set_p2d (dev, 0, VAS_EBOOT_CS5536_DESTINATION_USB, 0x05020000);
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set_p2d (dev, 1, VAS_EBOOT_CS5536_DESTINATION_USB, 0x05022000);
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set_p2d (dev, 5, VAS_EBOOT_CS5536_DESTINATION_USB, 0x05024000);
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set_p2d (dev, 6, VAS_EBOOT_CS5536_DESTINATION_USB, 0x05023000);
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{
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volatile VasEBoot_uint32_t *oc;
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oc = VasEBoot_absolute_pointer (VasEBoot_pci_device_map_range (dev, 0x05022000,
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VAS_EBOOT_CS5536_USB_OPTION_REGS_SIZE));
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oc[VAS_EBOOT_CS5536_USB_OPTION_REG_UOCMUX] =
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(oc[VAS_EBOOT_CS5536_USB_OPTION_REG_UOCMUX]
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& ~VAS_EBOOT_CS5536_USB_OPTION_REG_UOCMUX_PMUX_MASK)
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| VAS_EBOOT_CS5536_USB_OPTION_REG_UOCMUX_PMUX_HC;
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VasEBoot_pci_device_unmap_range (dev, oc, VAS_EBOOT_CS5536_USB_OPTION_REGS_SIZE);
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}
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/* Setup IDE controller. */
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_IDE_IO_BAR,
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VAS_EBOOT_CS5536_LBAR_IDE
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| VAS_EBOOT_CS5536_MSR_IDE_IO_BAR_UNITS);
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_IDE_CFG,
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VAS_EBOOT_CS5536_MSR_IDE_CFG_CHANNEL_ENABLE);
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_IDE_TIMING,
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(VAS_EBOOT_CS5536_MSR_IDE_TIMING_PIO0
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<< VAS_EBOOT_CS5536_MSR_IDE_TIMING_DRIVE0_SHIFT)
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| (VAS_EBOOT_CS5536_MSR_IDE_TIMING_PIO0
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<< VAS_EBOOT_CS5536_MSR_IDE_TIMING_DRIVE1_SHIFT));
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VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING,
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(VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_CMD_PIO0
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|
<< VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_CMD_SHIFT)
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| (VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_PIO0
|
|
<< VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_DRIVE0_SHIFT)
|
|
| (VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_PIO0
|
|
<< VAS_EBOOT_CS5536_MSR_IDE_CAS_TIMING_DRIVE1_SHIFT));
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|
|
|
/* Setup Geodelink PCI. */
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|
VasEBoot_cs5536_write_msr (dev, VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL,
|
|
(4ULL << VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL_OUT_THR_SHIFT)
|
|
| (4ULL << VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL_IN_THR_SHIFT)
|
|
| (8ULL << VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL_LATENCY_SHIFT)
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|
| VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL_IO_ENABLE
|
|
| VAS_EBOOT_CS5536_MSR_GL_PCI_CTRL_MEMORY_ENABLE);
|
|
|
|
/* Setup windows. */
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|
set_io_space (dev, 0, VAS_EBOOT_CS5536_LBAR_SMBUS, VAS_EBOOT_CS5536_SMBUS_REGS_SIZE);
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|
set_io_space (dev, 1, VAS_EBOOT_CS5536_LBAR_GPIO, VAS_EBOOT_CS5536_GPIO_REGS_SIZE);
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|
set_io_space (dev, 2, VAS_EBOOT_CS5536_LBAR_MFGPT, VAS_EBOOT_CS5536_MFGPT_REGS_SIZE);
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|
set_io_space (dev, 3, VAS_EBOOT_CS5536_LBAR_IRQ_MAP, VAS_EBOOT_CS5536_IRQ_MAP_REGS_SIZE);
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|
set_io_space (dev, 4, VAS_EBOOT_CS5536_LBAR_PM, VAS_EBOOT_CS5536_PM_REGS_SIZE);
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|
set_io_space (dev, 5, VAS_EBOOT_CS5536_LBAR_ACPI, VAS_EBOOT_CS5536_ACPI_REGS_SIZE);
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|
set_iod (dev, 0, VAS_EBOOT_CS5536_DESTINATION_IDE, VAS_EBOOT_ATA_CH0_PORT1, 0xffff8);
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|
set_iod (dev, 1, VAS_EBOOT_CS5536_DESTINATION_ACC, VAS_EBOOT_CS5536_LBAR_ACC, 0xfff80);
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|
set_iod (dev, 2, VAS_EBOOT_CS5536_DESTINATION_IDE, VAS_EBOOT_CS5536_LBAR_IDE, 0xffff0);
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|
}
|